IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 17, NO. 3, MARCH 1998 239 Application of Genetically Engineered Finite-State- Machine Sequences to Sequential Circuit ATPG Michael S. Hsiao, Member, IEEE, Elizabeth M. Rudnick, Member, IEEE, and Janak H. Patel, Fellow, IEEE Abstract—New methods for fault-effect propagation and state justification that use finite-state-machine sequences are proposed for sequential circuit test generation. Distinguishing sequences are used to propagate the fault effects from the flip-flops to the primary outputs by distinguishing the faulty machine state from the fault-free machine state. Set, clear, and pseudoregis- ter justification sequences are used for state justification via a combination of partial state justification solutions. Reengineering of existing finite-state machine sequences may be needed for specific target faults. Moreover, conflicts imposed by the use of multiple sequences may need to be resolved. Genetic-algorithm- based techniques are used to perform these tasks. Very high fault coverages have been obtained as a result of this technique. Index Terms—Automatic test generation, genetic engineering, pseudoregisters, state justification. I. INTRODUCTION T HE MAJORITY of the time spent by automatic test generators for sequential circuits is used to find test sequences for hard-to-detect faults. These hard faults are either hard to excite, hard to propagate, or both. Deterministic test generators have been proposed in the past [1]–[12], but they require backtracing through complex gates and flip-flops, and remodeling of such primitives is often required. Simulation- based test generators, on the other hand, avoid the complexity of backtracing by processing in the forward direction only. However, simulation-based approaches often fall short when targeting the hard faults. Previously, homing, synchronizing, and distinguishing se- quences have been used to aid the test generator in improving the fault coverage [6], [10]–[12], [26]. In [6], [10], and [12], symbolic and state-table-based techniques were used to derive these sequences in the fault-free machine. In [6], cube intersections of ON/OFF-set representations were used to derive distinguishing sequences. Binary decision diagrams (BDD’s) and implicit state enumeration were used in [10] to derive synchronizing sequences. In the work by Park et al. [12], functional information was used to pregenerate sequences which simplified the propagation of fault effects from the flip- Manuscript received August 30, 1996. This work was supported in part by the Semiconductor Research Corporation under Contract SRC 95-DP-109, in part by DARPA under Contract DABT63-95-C-0069, and by Hewlett-Packard under an equipment grant. This paper was recommended by Associate Editor S. Reddy. M. S. Hsiao is with the Department of Electrical and Computer Engineering, Rutgers, the State University of New Jersey, Piscataway, NJ 08854-8058 USA. E. M. Rudnick and J. H. Patel are with the Center for Reliable and High-Performance Computing and Department of Electrical and Computer Engineering, University of Illinois, Urbana, IL 61801 USA. Publisher Item Identifier S 0278-0070(98)03084-X. flops to the primary outputs, and state justification was done by using BDD’s. Since these sequences are generated using the fault-free machine only, they may become invalid in a faulty machine. Homing sequences composed of specifying and distinguishing portions were used to aid ATPG in [11], but they had to be recomputed for each target fault. The presence of a fault creates a faulty machine (circuit structure) which differs from the fault-free machine. The goal is to distinguish the faulty machine from the fault-free machine by activating the target fault and propagating its effects to the primary outputs. With the test generation process divided into fault activation and fault propagation phases, the principal approach taken in our work is to use finite-state- machine sequences in as many places as possible to reduce the work of rediscovering such sequences. The finite-state- machine sequences used in this work encompass distinguishing sequences, set/clear sequences, and justification sequences, all of which will be explained in the subsequent sections. No state diagrams are needed in this work. Several questions remain. Since there are many finite-state- machine sequences for any large machine, what finite-state- machine sequences should be generated and stored? Sequences derived for a fault-free machine may not be valid for a faulty machine, or they may be valid for some faulty machines, but not for other faulty machines; how can invalid sequences be used to fit the specific needs of the target fault? Moreover, A finite-state-machine sequence may not always exist; can partial sequences be used? Finally, we cannot indiscrimi- nately generate large numbers of sequences because potential problems of excessive storage and execution may result. In this work, several classes of finite-state-machine se- quences are generated statically for the fault-free machine, and also captured dynamically for the fault-free and faulty machines during the test generation process. The difficulty of deriving a sequence is taken into account at run time in the computation of flip-flop controllability and observability. These measures are much more accurate than the conven- tional controllability and observability metrics. They help to guide the test generator much more effectively, e.g., in propagating fault effects to flip-flops that are easy to observe. Modifications to the finite-state-machine sequences may be needed before they can be applied to fault propagation or state justification, and several useful sequences may exist for a particular problem. Genetic algorithms (GA’s) [14] have been demonstrated to be effective in combining useful portions of several candidate solutions to a given problem. Therefore, we have chosen to use genetic algorithms in this work, both to 0278–0070/98$10.00  1998 IEEE