678 0-7803-7169-0/01 $10.00 © 2001 IEEE Paper 25.1 ITC INTERNATIONAL TEST CONFERENCE On Efficient Error Diagnosis of Digital Circuits Nandini Sridhar * Michael S. Hsiao † Intel Corporation Bradley Dept. of ECE, Virginia Tech Dupont, WA 98327 Blacksburg, VA 24061 nandini.sridhar@intel.com mhsiao@vt.edu Abstract The rising trend in large scale integration and design complexity has greatly increased the need for efficient de- sign error diagnosis. We present techniques for fast and efficient error diagnosis of digital circuits by eliminat- ing to a large extent the set of false candidates identified by the diagnosis. The elimination of false candidate re- gions is conducted via distinguishing X’s, flipping of val- ues at the output of candidate regions, and combination of these techniques. Our algorithms help to improve both the speed and resolution of error diagnosis. Experimen- tal results on combinational benchmark circuits showed that up to 92% improvement in diagnostic resolution and 74% speedup over the original region-based diagnosis can be achieved with our approaches. 1 Introduction Errordiagnosisoccursearlyinthedesignflowbeforethe actualchipisfabricated. Itisinvokedonceaverification tool has identified that the the design implementation does not conform to the specification. This is due to errors introduced during the design process. The com- plexity of present day designs makes it cumbersome for the designer to locate these errors manually. Thus, ef- ficient automatic error diagnosis tools can be extremely helpful to the designer in providing feedback about po- tential error sites in the circuit. Only these sites need be targeted for correction of the implementation. Venerisetal.[1,2]presentedanefficientapproachfor Design Error Detection and Correction(DEDC) based ontestvectorsimulationandBooleanfunctionmanipu- lation. Theerrorlocationandcorrectionalgorithmpro- vides a list of all possible actual and equivalent single modification locations along with their respective cor- rections. Abadir et al. [3] presented a single design er- ror model for the DEDC problem, a subset of which is used in most cases of DEDC [4] and [5]. Pomeranz and * Formerly with Dept. of ECE, Rutgers University † Supported in part by an NSF Career Award, under contract CCR-0093042, NSF grant CCR-0098304, and NJ Commission on Science & Technology. Formerly with Rutgers. Reddy [6,7], proposed test vector simulation methods for the DEDC problem. However, their method did not alwaysguaranteeasolutionandwasdemonstratedonly on small circuits. Tomita et al. [8,9] proposed the use of IPLDEs (input pattern for locating design errors) for bothsingleandmultipleerrors. AymanWahbaandDo- miniqueBorrione[10]presentedanefficienttechniqueto localize connection errors in combinational circuits. To do so, they generated special test patterns that could rapidly locate the error. Some of the earlier work car- riedoutinerrordiagnosispresentedin[11–13]dealtonly with gate errors. Other techniques such as [6,9] dealt withgateconnectionerrorstoo,butwerelimitedinthat they were not precise in locating the error and used a fairly large number of test patterns to locate the error. Huang et al. [14] presented techniques for diagnosis for both sequential and combinationalcircuits by extensive enumerationandsimulation. Insomeerrormodelbased approaches such as [15,16], after the diagnosis is com- pleted, the error is matched with an error type in the model and the implementation is rectified accordingly. A general model for both fault and error diagnosis was proposed by Boppana et al. [17] and has been used toeffectivelydiagnosesingleerrorsincombinationalcir- cuits. The model was then extended to locate multiple errorsandusedtheconceptoflocality(Region-baseder- rormodel)[18,19]. ThisworkwasfurtheredbyD’Souza et al. [20] to tackle diagnosis of sequential circuits. Inthiswork,wepresentthreealgorithmstoperform enhanced error diagnosis by eliminating as many false candidates as possible from an initial list of candidate error regions obtained from the original region-based model. Experiments are conducted on ISCAS85 com- binational benchmark circuits and the results indicate that up to 92% improvement in diagnostic resolution and74%speedupovertheoriginalregion-baseddiagno- sis can be achieved with our approaches. Therestofthispaperisorganizedasfollows. Section 2 gives an overview of the region-based model and ter- minologies. Section 3 explains the proposed algorithms for eliminating false candidates. Section 4 discusses ex- perimental results, and Section 5 concludes the paper. Proceedings of the International Test Conference 2001 (ITC’01) 0-7803-7171-2/01 $17.00 © 2001 IEEE