International Test Conference, 1999. pp. 858-867 An Integrated Approach to Behavioral-Level Design-For-Testability Using Value-Range and Variable Testability Techniques Sandhya Seshadri † and Michael S. Hsiao ‡ † Mentor Graphics Corporation, Warren, NJ ‡ Department of Electrical & Computer Engineering, Rutgers University, Piscataway NJ Abstract This research applies formal dataflow analysis and tech- niques to high-level DFT. Our proposed approach improves testability of the behavioral-level circuit description (such as in VHDL) based on propagation of the value ranges of variables through the circuit’s Control-Data Flow Graph (CDFG). The resulting testable circuit is accomplished via controllability and observability computations from these value ranges and insertion of appropriate testability en- hancements, while keeping the design area-performance overhead to a minimum. I Introduction Traditionally, VLSI design and test processes have been kept separate, with test considered only at the end of the design cycle. However, in contemporary design flows, test merges with design much earlier in the process, creating a design-for-test (DFT) process flow, the goal of which is to produce hierarchically testable designs. A design is said to be hierarchically testable, if the input (output) ports of ev- ery module in the design hierarchy, are easily controllable (observable) through system inputs (outputs) [1]. Classical DFT strategies have been conventionally lim- ited to the end of the design phase, when a detailed gate- level description of the design is available [6, 7, 8]. Testa- bility features that are incorporated into the design at the post-synthesis step result in area and delay penal- ties. These structural testability enhancement techniques fall into the following categories: Built-in self-test (BIST), non-scan and scan- based DFT. In general, the amount of scan required to get an acceptable fault coverage varies from design to design. At-speed testing of a circuit is not possible when scan tests are used, due to scanning in and out of flip-flop values. Recent studies [1, 2, 3, 4, 5, 13, 15] have shown that if testability is not addressed during behavioral synthe- sis, many modules and registers in the resultant register- transfer-level (RTL) circuit may not be testable for the op- erations and/or variables mapped to them. The problem is exacerbated in the presence of loops, constants and re- convergent fanout in the control-data flow graph (CDFG) corresponding to the design. In [9], the authors proposed a partial-scan selection mechanism that works on the CDFG of a design derived from its behavioral description. Hard-to-test areas of the design are identified by the evaluated controllability and observability measures, and test point insertion techniques such as those described in [5] are applied. Lastly, flip-flops corresponding to variables that are hard to control and ob- serve are selected for partial-scan to maximize the impact on testability of the design. The controllability measures obtained in this fashion, however, do not consider the value ranges of the variables and the probabilities of propagating these value ranges to the nodes in the CDFG. In [17], the authors propose a behavioral testability enhancement tech- nique based on the analysis of values and variable probabil- ities obtained from profiling of the high-level description. The simulations conducted during profiling would have to be exhaustive in order to obtain all of the values and their probabilities for every variable. The contribution of our work is to enhance the testabil- ity of a behavioral-level design by accurately pin-pointing the hard-to-test regions of the circuit based on an entirely new approach involving a formal dataflow analysis, rather than by inspection or profiling. The improved accuracy of the controllability and observability measures of the vari- ables are a result of applying a value range propagation technique [10, 11, 14, 16]. Although the techniques used in [10, 11, 14, 16] were developed to improve the accuracy of static value and branch prediction in compilers, we have observed that they can be adapted in our DFT work. A is initialized here A := A + 1 Y := f(A) Z := g(Y) Loop Exit Figure 1: A Simple Example Figure 1 shows an example of a variable A incremented within a loop in the high-level description. The variables Y and Z are defined to be functions of A and Y, respectively, inside the loop. Variable Y can be hard to control to any specific value if the function f () is non-trivial. Similarly,