The Memory Structures of ATLAS I, a High Performance, 16x16 ATM Switch Supporting Backpressure. Dionisios Pnevmatikatos, Georgios Kornaros, George Kalokerinos, and Chara Xanthaki Institute of Computer Science (ICS) Foundation for Research and Technology - Hellas (FORTH) Science and Technology Park of Crete, Vassilika Vouton, P.O.Box 1385, Heraklion, Crete, GR 711 10 Greece {pnevmati, kornaros, george, xanthaki}@ics.forth.gr Abstract We present the overall structure of ATLAS I, emphasizing the memory use and requirements. We categorize these requirements in functionality and bandwidth and present the solutions we used in the first implementation of ATLAS I in a 0.35  CMOS technology. This implementation can serve as a starting point in the design of future switches with functionality similar to ATLAS I. 1. Introduction ATLAS I is a general-purpose, single-chip ATM switch with advanced architectural features. It is being developed within the ASICCOM 1 project. Figure 1 presents an overview of ATLAS I; it is a highly integrated 16x16 switch, with point-to-point serial links running at 622 Mbits/s each. Using link bundling, ATLAS I can also be configured as 8x8 at 1.25Gbps/link, or 4x4 at 2.5 Gbps/link, etc. The links run ATM on top of IEEE Std. 1355 “HIC/HS” [HIC95] as physical layer, using the BULL “STRINGS” GBaud serial-link transceiver [MCLN93]. 1 Funded by the European Union ACTS (Advanced Communication Technologies and Services) Programme. Internally, ATLAS I operates as a crossbar, with a 256-cell shared buffer and implements three levels of priority, each level having its own queues. Fifty-one output queues (3×16 outputs plus 1 management port) and 3 multicast queues are (logically) maintained in the shared buffer. ATLAS I provides (optional) credit-based flow control (backpressure), using a protocol that resembles QFC [QFC95]. A cell in a backpressured service class (priority level) is never dropped. It can only be transmitted if it acquires both a buffer-pool credit for its outgoing link (indicating that sufficient buffer space exists at the receiver side) and a flow-group credit for its connection. A flow group is merely a set of connections that are flow- controlled together; ATLAS I supports up to 4096 flow groups per link. Credits are transmitted on the links using 1 control and 3 data characters. Our evaluation of the credit- based flow control has shown its superior performance, especially in isolating connections from bursty and hot spot traffic [KaSS98], justifying its implementation cost. These advantages are underlined by other researchers that propose and implement multilane backpressure for ATM switches [QFC95][OzSV95][KuBC94]. The control section of ATLAS I is shared among all links and the entire switch operation is pipelined and functions at the rate of one event per clock cycle. Asynchronous events such as cell arrivals are serialized and handled one at a time. ATLAS I operates in a period of 33 clock cycles: 16+16 to service input and output events and one extra cycle for switch management functions. The clock cycle of the switch core is 20 nanoseconds, and was determined to be fast enough to handle the full bandwidth of the serial- link transceivers. ATLAS I will be fabricated in a 0.35 micron CMOS process, inside a 225 mm 2 die, by SGS Thomson, Crolles, France. More details on the internal organization of the chip and our experiences of the design can be found in [KaSV96], [KKVK97], and [Vats98]. This paper systematically presents the main memory structures of ATLAS I. These structures are more influenced by functionality rather than implementation choices, and can serve as a reference point in the design of Figure 1: ATLAS I chip overview