Tracking Uncertainty with Probabilistic Logic Circuit Testing Smita Krishnaswamy, Igor L. Markov, and John P. Hayes University of Michigan &THE EVOLUTION OF IC technology has included changes, sometimes subtle ones, in the types of defects prevalent in circuits. Therefore, designers must occa- sionally reconsider fault modeling and testing in order to incorporate relevant new sources of circuit error. At the deep-submicron scale, VLSI circuits have higher feature density, lower supply voltage, and higher operating frequency, all contributing to greater signal noise. High feature density increases capacitive and inductive crosstalk between neighboring signals, which can result in delay and logic faults. Further- more, process variations are more common because of the discrepancy between lithography wavelengths and circuit feature sizes. These phenomena lead to a considerable amount of randomness in actual threshold voltages and gate delays observed after manufacturing. Decreased threshold voltages leave circuits suscep- tible to soft faults caused by external radiation. When primary radiation particles enter the atmosphere, neutrons and other secondary particles can strike a critical circuit node, leaving behind an ionized track in silicon, called a single-event upset. An SEU can flip a gate’s output signal. If this effect propagates to a flip- flop, that flip-flop can capture (latch) it, forming a soft, but persistent, error. However, because of three masking mechanisms, not all SEUs cause circuit errors: An SEU is logically masked if it appears in an unsensitized portion of the circuit. It is electrically masked if its amplitude becomes lower than the threshold voltage as it propagates through a gate. Temporal masking occurs if an SEU arrives at a flip-flop during a nonlatching portion of the clock cycle. The proba- bility of an SEU at a gate depends on gate area, neu- tron flux, altitude, and other environmental factors. 1 New device technologies such as quantum and nanocircuits exhibit probabilistic behavior because the scale of interaction is often that of subatomic particles. For instance, quantum bits exist in superpo- sition states that collapse to either 0 or 1 with different probabilities upon measurement. In many nanoelec- tronic devices, the difference between logical states approaches the thermal limit. The behavior of such devices will therefore be inherently probabilistic. Furthermore, defects become more common in nanoscale devices because of manufacturing difficul- ties. For example, devices such as single-electron transistors and quantum cellular automata store state in a few electrons, so missing electrons and misplaced cells are common faults in these devices. Additionally, electromagnetic noise and other types of interference affect nanoscale systems easily. In summary, most defects in nanocircuits are either inherently probabi- listic or modeled probabilistically when deterministic models are impractical. Several soft-error-rate analyzers have been released recently. 2,3 These tools electrically characterize specif- ic technology nodes and estimate the overall error rate of combinational circuits. However, they are difficult to use for ATPG because they don’t offer discrete logic- 312 Editor’s note: The diverse nature of the faults and defects that may occur at nanoscale ranges necessitates new techniques for ATPG. This article proposes an efficient technique that relies on a probabilistic approach to detect and diagnose nontraditional faults and defects. —Fabrizio Lombardi, Northeastern University Computer-Aided Design for Emerging Technologies 0740-7475/07/$25.00 G 2007 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers