Solving Difficult Instances of Boolean Satisfiability in the Presence of Symmetry ∗ Fadi A. Aloul, Arathi Ramani, Igor L. Markov and Karem A. Sakallah Department of EECS, University of Michigan, Ann Arbor 48109-2122 {faloul,ramania,imarkov,karem}@eecs.umich.edu April 29, 2003 Abstract Research in algorithms for Boolean satisfiability (SAT) and their implementations [11, 45, 50] has recently outpaced benchmarking efforts. Most of the classic DIMACS bench- marks [22] can now be solved in seconds on commodity PCs. More recent benchmarks [60] take longer to solve due to their large size, but are still solved in minutes. Yet, relatively small and difficult SAT instances must exist if P=NP. To this end, our work articulates SAT instances that are unusually difficult for their size, including satisfiable instances derived from Very Large Scale Integration (VLSI) routing problems. With an efficient implementa- tion to solve the graph automorphism problem [43, 55, 56], we show that in structured SAT instances difficulty may be associated with large numbers of symmetries. We point out that a previously published symmetry extraction mechanism [19] based on a reduction to the graph automorphism problem often produces many spurious symmetries. Our work contributes two new reductions to graph automorphism, which extract all correct symmetries found previously [19] as well as phase-shift symmetries not found earlier. The correctness of our reductions is rigorously proven, and they are evaluated empirically. We also formulate an improved construction of symmetry-breaking clauses in terms of permutation cycles and propose to use only generators of symmetries in this process. These ideas are implemented in a fully automated flow that first extracts symmetries from a given SAT instance, pre-processes it by adding symmetry-breaking clauses and then calls a state- of-the-art backtrack SAT solver. Significant speed-ups are shown on many benchmarks versus direct application of the solver. In an attempt to further improve the practicality of our approach, we propose a scheme for fast “opportunistic” symmetry extraction and also show that considerations of symmetry may lead to more efficient reductions to SAT in the VLSI routing domain. ∗ Early results of this work were reported at the ACM/IEEE Design Automation Conference in June 2002. 1