748 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 24, NO. 5, MAY 2005 Mixed Block Placement via Fractional Cut Recursive Bisection Ameya Ramesh Agnihotri, Satoshi Ono, Chen Li, Student Member, IEEE, Mehmet Can Yildiz, Ateen Khatkhate, Cheng-Kok Koh, Member, IEEE, and Patrick H. Madden, Member, IEEE Abstract—Recursive bisection is a popular approach for large scale circuit placement problems, combining a high degree of scal- ability with good results. In this paper, we present a bisection-based approach for both standard cell and mixed block placement; in contrast to prior work, our horizontal cut lines are not restricted to row boundaries. This technique, which we refer to as a fractional cut, simplifies mixed block placement and also avoids a narrow re- gion problem encountered in standard cell placement. Our imple- mentation of these techniques in the placement tool Feng Shui 2.6 retains the speed and simplicity for which bisection is known, while making it competitive with leading methods on standard cell de- signs. On mixed block placement problems, we obtain substantial improvements over recently published work. Half perimeter wire lengths are reduced by 29% on average, compared to a flow based on Capo and Parquet; compared to mPG-ms, wire lengths are re- duced by 26% on average. Index Terms—Circuit placement, design automation, mixed size placement, placement legalization, recursive bisection. I. INTRODUCTION A DVANCING fabrication processes have enabled ever in- creased circuit sizes. This has resulted in an explosion in the number of logic gates in typical designs, and an industry need for placement methods that can handle millions of mov- able objects. At the same time, design cycle times have shrunk; time-to-market pressure has put a premium on speed for design automation tools. In many respects, circuit designers are at a computational dis- advantage; while available computing resources increase at a rate comparable to the size of the circuits, the underlying algorithms used in the design tools are seldom linear with problem size. With each technology generation, the size of the problems double, as does the speed of the computers used to solve the problems; un- fortunately, the problems are more than a factor of two harder. Manuscript received June 15, 2004; revised September 8, 2004. This work was supported in part by the Semiconductor Research Corporation under Project 947.1, in part by an IBM Faculty Partnership Award, in part by an equipment grant from Intel, and in part by the New York State Microelectronics Design Center. This paper was recommended by Guest Editor L. Scheffer. A. R. Agnihotri is with the Computer Science Department, State University of New York, Binghamton, NY 13902 USA. S. Ono and P. H. Madden are with the Department of Information and Media Sciences, University of Kitakyushu, Kitakyushu 808-0135, Japan, on leave from the Computer Science Department, State University of New York, Binghamton, NY 13902 USA(e-mail: pmadden@cs.binghamton.edu). C. Li and C.-K. Koh are with the School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907 USA (e-mail: li35@ecn.purdue.edu; chengkok@ecn.purdue.edu). M. C. Yildiz is with the IBM Austin Research Lab, Austin, TX 78758 USA. A. Khatkhate is with Lockheed-Martin, Owego, NY 13827 USA. Digital Object Identifier 10.1109/TCAD.2005.846363 To deal with the increasing challenge, circuit designers have a number of techniques. Foremost is heirarchy: A large design is divided into smaller components with individual solutions being assembled to form the whole. By breaking a large problem into smaller ones, a design becomes more tractable—but at the ex- pense of optimization potential. While many would advocate that designs should be as flat as possible, it is clear that some degree of heirarchy is necessary. A second technique for dealing with the increasing challenge is to shift toward algorithmic approaches that have better scalability. For circuit placement, simulated annealing is well known to produce exceptional results—but with a heavy run time penalty. Across the industry, there has been an implicit acceptance of reduced quality, in exchange for better run times. Most commercial design automation tool vendors utilize ana- lytic or bisection based placement methods; if a design is late to market, the ultimate quality is largely irrelevant. In this paper, we present the placement tool Feng Shui 2.6, which combines a simplification of the recursive bisection approach [5] and support for mixed block designs [25]. The ap- proach is scalable to large designs and computationally efficient. Our improvements allow us to obtain reduced wire lengths, making the tool competative with a well respected annealing based approach on standard cell designs. For designs with a mix of standard cells and macro blocks—commonly known as the “mixed block” or “boulders and dust” problem—we obtain the best published wire length results, improving by 26% on average over the closest comparable tool. In this paper, our primary focus will be on mixed block design. Our main contributions are the development of a fractional cut approach, and a complementary legalization algorithm. In recursive bisection, horizontal cut lines are normally aligned with cell row boundaries—this places a number of constraints on the partitioning engine. Legalization for bisection based ap- proaches is usually trivial; new horizontal cut positions require a more sophisticated approach. We take advantage of the uniform distribution of cell area that results from our bisection based ap- proach, and develop a legalization method that is efficient and of extremely high quality. The legalization method is based on prior work by Hill [18]. The remainder of this paper is organized as follows. We first briefly survey traditional placement problems, and consider prior placement techniques. We next describe our fractional cut approach, and provide an explanation of how we legalize placements. Experimental results show the dramatic improve- ment in wire length our methods have produced. We conclude the paper with a summary of current and future work. 0278-0070/$20.00 © 2005 IEEE Authorized licensed use limited to: Purdue University. Downloaded on July 9, 2009 at 11:32 from IEEE Xplore. Restrictions apply.