On-chip networks: A scalable, communication-centric embedded system design paradigm J¨ org Henkel , Wayne Wolf and Srimat Chakradhar NEC Laboratories America, Princeton, NJ Princeton University, Princeton, NJ Abstract As chip complexity grows, design productivity boost is ex- pected from reuse of large parts and blocks of previous de- signs with the design effort largely invested into the new parts. More and more processor cores and large, reusable compo- nents are being integrated on a single silicon die but reuse of the communication infrastructure has been difficult. Buses and point to point connections, that have been the main means to connect components on a chip today, will not result in a scalable platform architecture for the billion transistor chip era. Buses can cost efficiently connect a few tens of com- ponents. Point to point connections between communication partners is practical for even fewer components. As more and more components are integrated on a single silicon die, per- formance bottlenecks of long, global wires preclude reuse of buses. Therefore, scalable on-chip communication infrastruc- ture is playing an increasingly dominant role in system-on- chip designs. With the super-abundance of cheap, function- specific IP cores, design effort will focus on the weakest link: efficient on-chip communication. Future on-chip communication infrastructure will overcome the limits of bus-based systems by providing higher band- width, higher flexibility and by solving the clock skew prob- lem on large chips. It may, however, present new problems: higher power consumption of the communication infrastruc- ture and harder-to-predict performance patterns. Solutions to these problems may result in a complete overhaul of SOC design methodologies into a communication-centric design style. The envisioning of upcoming problems and possible benefits has led to intensified research in the field of what is called NoCs: Networks on Chips. The term NoCs is used in a broad meaning, encompassing the hardware communication infrastructure, the middleware and operating system commu- nication services, and a design methodology and tools to map applications onto a network on chip. This paper discusses trends in system-on-chip designs, critiques problems and op- portunities of the NoC paradigm, summarizes research activ- ities, and outlines several directions for future research. 1 Current Trends in SoC Complexity By the end of this decade, silicon technology will allow chip complexities of up to 1 billion transistors on a single piece of silicon (see [5]). The embedded systems market will es- pecially profit from this development since we can virtually build a whole system (processing elements, memories, com- munication infrastructure, analog I/O etc) on one chip (SoC). Though a large part of these transistors may be used in embed- ded memory, a significant share will be used for increasing the number of on-chip processing units in order to increase system performance. Assuming the complexities of today’s state-of-the-art embedded processors (e.g. [2]), several hun- dreds or even thousands of embedded processors can fit on a single chip. Today’s complex SoCs comprise of hardly more than 10-15 processors on a single chip (example: [3]). Unfortunately, we 55 50 47 43 32 25 20 10 8 3 2 1 0.8 0.4 0.3 0.2 0 50 100 150 200 250 300 Available Gates Used Gates Millions of Gates (source: G. Smith, Gartner/Dataquest, 2003) 1990 1992 1994 1996 1998 2000 2002 2004 2006 Design Productivity Gap Figure 1: Chip complexity and design complexity crisis [1] are unable to exploit the maximum possible amount of transis- tors (silicon-technology-wise) per chip. This fact is even more obvious when the number of transistors per SOC without the embedded memory (i.e. in the absence of easy to design reg- ular structures) is excluded. Clearly, real-world SOCs’ com- plexities currently (2003) lag behind the capabilities of current silicon technologies even though there is certainly a demand for higher complexities from an application demand point of view. Fig. 1[1] gives a possible answer: it shows the predicted pro- ductivity gap. It is measured as the number of available gates per chip for a given silicon technology for SOCs on the one side (red graph) and the number of actually used gates per chip for a given silicon technology on the other side (blue graph). The gap is predicted assuming that no ESL (Electronic Sys- tem Level Design) methodologies are deployed for designing future complex SOCs. In other words: the Design gap might be avoided if more ESL methodologies would be deployed in all areas of system level design like specification/modeling, synthesis etc. However, with current activities in ESL methodologies, we think this gap will actually be closed and thus will indeed al- low the system designer to integrate all 1 billion transistors on a single chip (see also [4]) as silicon technology provides these potential complexity by the end of the decade. Application areas for 1-billion-transistor SoCs are manifold ranging from security systems (e.g. video surveillance), con- trol systems (e.g. automotive control), individual health sys- tems (e.g. hearing aids) to main stream consumer products in such areas as personal communication (e.g. cell phones), per- sonal computing (e.g. PDA), entertainment (e.g. MP3 play- ers), video/photo (e.g. digital still/video cameras) and many more. It can be observed that many of these devices feature already today a high complexity with a rising tendency as new device generation feature a larger functionality and hence need a more complex SoCs for their implementation. This trend will significantly change the way SoCs are de- signed, both from a design methodology point of view (not covered in this article) as well as from an architectural point Proceedings of the 17th International Conference on VLSI Design (VLSID’04) 1063-9667/04 $ 20.00 © 2004 IEEE