Vol 04, Issue 01; January-February 2013 International Journal of VLSI and Embedded Systems-IJVES http://ijves.com ISSN: 2249 – 6556 2010-2012 – IJVES Indexing in Process - EMBASE, EmCARE, Electronics & Communication Abstracts, SCIRUS, SPARC, GOOGLE Database, EBSCO, NewJour, Worldcat, DOAJ, and other major databases etc., 196 VLSI Implementation and Comparative Analysis of Memory BIST Controller using March Algorithm B P SAHU 1 , A K MOHANTY 2 , S S MAHATO 3 Department of Electronics and Communication Engineering, National Institute of Science and Technology, Berhampur, Odisha, India 1 biswa_nath_sahu@yahoo.co.in , 2 ajit.mohanty07@rediffmail.com , 3 satyamahato@yahoo.com ABSTRACT With the advent of deep-submicron VLSI technology, core-based System on chip design is attracting an increasing focus. For this progress it is possible to integrate huge embedded memory core into a singe chip. However to offer a test solution for the on-chip memory cores is a crucial job. In this paper we present a comparative study on memory BIST Controller using different march algorithm by implementing that in cadence Tool. Finite state machines (FSM) are design to implement march based Test algorithm. From the comparison of eight March algorithm, March Y is the better algorithm in terms of area, power and complexity than the other March algorithm. Keywords: Built-In Self-Test, March Algorithm, Memory Under Test RTL and System-on-Chip. 1. INTRODUCTION In modern SoCs, embedded memories occupy the largest part of the chip area and include an even larger amount of active devices. As memories are designed very densely to the limits of the technology they might be causes to failures than logic. In addition, defect types are becoming more complex and diverse and may escape detection during fabrication test. The above two trends increase defect level and affect circuit quality periodically. The memory test algorithms should evolve to cover the fault models corresponding to the target fabrication process and memory design. These fault models may not be known completely during at the design of a product, hence the need for a flexible test approach allow selecting the memory test algorithm. This flexibility has to be integrated in memory BIST, which is the mainstream test technology for embedded memories [1]. Embedded memory on Systems On-Chip (SOCs) can create a significant test issues due to its integration and closeness to logical cores. It was predicted that in Application-Specific Integrated Circuits (ASICs) embedded memory will occupy 94% of die area. In this technique a suitable BIST architecture is a vital issue to produce yield. The combination of a flexible memory BIST engine, which allows custom variations to the test algorithms, with enhanced at-speed application provides the basis for ensuring high-quality testing. This is increasingly important considering the trend toward designs with more memory as compare to the logic [2]. Built-In Self-Test (BIST) technique was a promising method for different types of test problems. In the memory BIST (MBIST) technology, there was a dedicated BIST controller which is used to implement a specific memory test algorithm when the chip under test (CUT) is in test mode [3]. In semiconductor memory technologies we have resulted in a very high density embedded memories. The number of memory cell per chip has increased rapidly day by day. From 1982 to 2006, the number of memory cells per chip has increased more than 1 Gigabyte in size resulting in a more complicated architecture. The larger capacity of RAM will introduce more physical failure as a result due to crosstalk between closely packed cells. As a result, high capacity memory size will produce more defects during system-on-chip (SOC) manufacturing that can be lead to yields reduction. Therefore, the semiconductor industry is facing with a new challenge to test and diagnose failures defects that occurs in high capacity memories. Hence, SRAM memories is one of the most used in the embedded system due to the faster operation compared to other memory types such as DRAM and DDRAM. Investigation on SRAM testing is needed to be explored in terms of test algorithms such as March Test Algorithm (MTA). The efficiency of MTA is based on how many write (w) and read (r) operation are applied to the SRAM to detect and diagnose the CFs. With this efficiency, it promises better results on faults detection and diagnosis [4]. In this paper, we implement FSM-based Memory BIST architecture which is a controller by different March algorithm. The March algorithm are implemented and verified by Cadence tool. The architecture is modelled and synthesized using resister transfer level (RTL) abstraction. After synthesized we present a comparative view of all March algorithm in term of area, power and complexity. The remaining part of the paper is organized as follow. In the next section, the memory fault and defect are discussed. Section 3 discusses the algorithm and test methods. Section 4 describes how Memory BIST controller is design and implemented using verilog hardware description language while Section 5 describes result of this paper and section 6 concludes the paper with future enhancement.