MODELING OF THE LEAKAGE DRAIN CURRENT IN ACCUMULATION-MODE SOI pMOSFETs FOR HIGH-TEMPERATURE APPLICATIONS M. Bellodi 1 , B. Iniguez 2 , D. Flandre 2 and J. A. Martino 1 1 Laboratório de Sistemas Integráveis, Universidade de São Paulo, LSI / PSI / USP, Av. Prof. Luciano Gualberto, trav. 3, 158 - 05508-900, São Paulo, SP, Brazil Fax: +55-11-3818-5665, E-mail: bellodi@lsi.usp.br 2 Université Catholique de Louvain - UCL, Belgium INTRODUCTION Nowadays, SOI CMOS technology is considered as the most suitable candidate for Integrated Circuits fabrication for high-temperatures applications (1), due to the drastic reduction of leakage currents at elevated temperatures when compared to the conventional CMOS technology (2). The aim of this work is to present a simple leakage drain current model for Accumulation- Mode SOI pMOSFETs operating from room up to 300 o C, based on an equivalent circuit using two pairs of diodes and one resistor, which physically represents the transistor channel behavior in the leakage region. Measurements, MEDICI (3) and PSPICE (4) simulators were used to support our derivation. EXPERIMENTAL AND MODEL RESULTS All measurements were performed in Accumulation- Mode SOI pMOSFETs with channel lengths L ranging from 1.0 to 20μm and channel width being 20μm .The gate oxide t oxF , silicon film t Si and buried oxide t oxB thickness are 32, 84 and 398nm, respectively. The leakage drain current I Leak was measured for all devices operating in the leakage region i.e., for the front gate voltage V GF equal to +1.0V, and for the back gate voltage V GB = 0V. The drain voltage V DS range is from 0 to -2.0V. Previous works (5,6) showed that the total drain leakage current I Leak in AM SOI pMOSFETs, is composed by a sum of three components ( front, body and back currents ) distributed along the silicon film thickness when the devices are operating up to 300 o C and for back gate bias V GB been higher than 0V. However, when these devices are biased with V GB =0V, the total leakage drain current I Leak is composed by the sum of two components only: a front current component that flows around the gate oxide / silicon film interface and a body current component. This composition is observed for all devices operating in linear and saturation regions and up to 300 o C. Using MEDICI we observed that the total drain leakage current mainly flows into the silicon film body. But when L increases, the body current component decreases due to the increase of the body resistance, whereas the front current component increases with the carrier generation volume. The front current becomes higher than the body current component for L higher than 10μm. To model the total drain leakage current as a function of the channel length L, temperature and mainly the drain voltage V DS , for the devices operating in the leakage region, each component behavior (front and body) was thoroughly analyzed by MEDICI simulations as a function of these parameters. It was concluded that the silicon volume where the front component flows, behaves as a pair of diodes connected face to face (D front ). In the PSPICE diodes models, we introduced the silicon film thickness variation (front component) since it changes according to the channel length. For the body component, after doing an accurate analysis, we concluded that this component can be represented by another pair of diodes connected face to face (D body ) in parallel with a resistor (R body ). This resistor takes into account the silicon film thickness where the body current flows (it decreases as L increases), and besides it, the channel length L. The body diodes also take into consideration the L influences on the saturation current, since it changes as the channel length increases. Figure 1 presents the complete leakage model proposed here for AM SOI pMOSFETs operating at high- temperatures. Figure 2 presents the comparison between some experimental and modeling results. +V GF -V DS D surf R body D body P+ P+ P- BOX Figure 1: The leakage drain current model proposed for the AM SOI pMOSFET operating at high-temperatures. 0,0 0,5 1,0 1,5 2,0 0 1x10 -8 2x10 -8 3x10 -8 4x10 -8 5x10 -8 6x10 -8 7x10 -8 L= 10.0 μ m L= 5.0 μ m L= 2.0 μ m Experimental data Model Results AM SOI pMOSFET T= 300 o C V GF = +1.0V V GB = 0V - I Leak [ A / μm ] - V DS [ V ] Figure 2: Experimental leakage drain current versus the model proposed for the AM SOI pMOSFET at 300 o C. CONCLUSIONS The present work illustrates a modeling for the leakage drain current in AM SOI pMOSFETs operating up to 300 o C. Good agreement was obtained between the experimental and the proposed model for all devices and temperature range analyzed. ACKNOWLEDGEMENTS Marcello Bellodi acknowledges FAPESP for the financial support. Denis Flandre is Senior Research Associate of the National Fund for Scientific Research (FNRS, Belgium). REFERENCES 1. D. Flandre, “High-Temperature Electronics”, IEEE Press, Ed. R. Kirschman, p. 303-308, 1998. 2. D. Jeon and D. E. Burk, IEEE Trans. Elec. Dev., 38, 2101, 1991. 3. TMA MEDICI: two- Dimensional Device Simulation Program, version 4.0, 1997. 4. OrCAD PSPICE A/D Basics, analogue / digital simulation program, version 8, OrCAD, 1997. 5. M. Bellodi and J. A. Martino, SOI - Tech. and Dev. IX, Electrochem. Soc. Proc. PV99-3, p.287, 1999. 6. M. Bellodi and J. A. Martino, ICMP’99, Technical Digest, p.298, 1999.