JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.11, NO.1, MARCH, 2011 DOI:10.5573/JSTS.2011.11.1.059 A Low Noise and Low Power RF Front-End for 5.8-GHz DSRC Receiver in 0.13 m CMOS Jaeyi Choi*, Shin-Hyouk Seo*, Hyunwon Moon**, and Ilku Nam* Abstract—A low noise and low power RF front-end for 5.8 GHz DSRC (Dedicated Short Range Commu- nication) receiver is presented. The RF front-end is composed of a single-to-differential two-stage LNA and a Gilbert down-conversion mixer. In order to remove an external balun and 5.8 GHz LC load tuning circuit, a single-to-differential LNA with capacitive cross coupled pair is proposed. The RF front-end is fabricated in a 0.13 m CMOS process and draws 7.3 mA from a 1.2 V supply voltage. It shows a voltage gain of 40 dB and a noise figure (NF) lower than 4.5 dB over the entire DSRC band. Index Terms—CMOS, DSRC, low noise, low power, RF front-end I. INTRODUCTION The dedicated short range communication (DSRC) system provides a communication between on board unit (OBU) and road side equipment (RSE) within a short range communication area. The electronic toll collection system (ETCS) is an application of DSRC system using 5.8 GHz ISM band and it provides driver’s convenience by eliminating traffic congestion. Korea and Japan currently adopt the 5.8 GHz DSRC system using amplitude shift keying (ASK) modulation. There are previously published literatures for the 5.8 GHz DSRC transceiver [1-7]. Most of them composed of hybrid modules, which are implemented in SiGe- BiCMOS process, are not compatible with CMOS digital modems [2-6]. Moreover, they used numerous external components, resulting in an increased cost and chip size. Recently, the trend of DSRC receiver design is to reduce chip size, cost, and power consumption, and to increase system feature and integration. Therefore, a low power low cost CMOS DSRC transceiver that can be integrated with a digital modem is necessary for this system. In this work, a CMOS RF front-end for the DSRC receiver is presented. The RF front-end is composed of a single-to-differential two-stage low noise amplifier (LNA) and a Gilbert down-conversion mixer. The DSRC RF front-end is implemented in a 0.13 m CMOS process. Section II describes the proposed balanced single-to-differential balun-LNA. The RF front-end circuits for DSRC receiver are described in Section III. Section IV presents the measurement results. Finally, Section V concludes this paper. II. PROPOSED BALANCED SINGLE-TO- DIFFERENTIAL BALUN-LNA Typically, a differential LNA is preferred in RF SoC (system on a chip) but this needs passive baluns to convert single-ended signal to differential signal. Passive baluns are too bulky to be integrated on a chip [8]. Therefore, it is desirable to use a single-ended input differential output LNA with high gain and low NF. Fig. 1(a) shows the conventional single-ended input differential output LNA. It adopts the common source (CS) amplifier with common gate common source (CGCS) balun as the single-to-differential converter. The small signal equivalent circuit of Fig. 1(a) is Manuscript received Dec. 2, 2010; revised Feb. 17, 2011. * School of Electrical Engineering, Pusan National University, Korea ** Samsung Electronics, Korea E-mail : nik@pusan.ac.kr