J Comput Electron (2007) 6: 439–444 DOI 10.1007/s10825-007-0153-7 Comprehensive approach to modeling threshold voltage of nanoscale strained silicon SOI MOSFETs M. Jagadesh Kumar · Vivek Venkataraman · Susheel Nawal Published online: 19 September 2007 © Springer Science+Business Media LLC 2007 Abstract A comprehensive approach for modeling the threshold voltage of nanoscale strained silicon-on-insulator (SSOI) and strained Si-on-SiGe-on-insulator (SSGOI) MOSFETs is presented. The model includes the effect of strain in terms of Ge mole fraction and various other de- vice parameters—channel length, channel doping, strained silicon film thickness, gate oxide thickness and gate work function. The accuracy of the proposed threshold voltage model is verified using two-dimensional numerical simula- tions. We have also demonstrated that our model can accu- rately predict the DIBL effects. Keywords Strained silicon · Silicon-on-insulator · MOSFET · Threshold voltage · Modeling and simulation 1 Introduction With each technology generation, device scaling has given rise to remarkable improvement in the performance of sil- icon MOSFETs. However, this trend is very unlikely to continue and new methods have to be explored for MOS- FET performance enhancement. Currently, strained-silicon devices are being seriously studied since they not only of- fer potential improvement in device performance but also are highly compatible with established silicon CMOS tech- nology. There are two types of strained silicon-on-insulator M.J. Kumar ( ) · S. Nawal Department of Electrical Engineering, Indian Institute of Technology, New Delhi 110016, India e-mail: mamidala@ieee.org V. Venkataraman Department of Electrical and Computer Engineering, Cornell University, Ithaca, NY 14850, USA Fig. 1 Cross-section of SSOI MOSFETs [1] (SOI) MOSFETs: (a) Strained silicon-on-insulator (SSOI) MOSFET [1] as shown in Fig. 1 and (b) strained Si-on- SiGe-on-insulator (SSGOI) MOSFET [2] as shown in Fig. 2. Strained silicon offers the advantage of enhanced mobility for electrons and holes and the insulator layer or buried ox- ide results in a low junction capacitance. The SSOI MOS- FET is free from some of the difficulties associated with the fabrication of SSGOI MOSFET. While both the above de- vices have been demonstrated experimentally, there is no unified analytical model for the threshold voltage of the above two devices. Based on the author’s previous work [1, 2], this paper provides a comprehensive approach to developing a unified analytical model for the threshold voltage of both the SSOI and SSGOI MOSFETs incorporating the effects of strain, silicon film thickness, channel length, channel doping and gate work function. The accuracy of the model is verified by comparing the model results with those obtained from two-dimensional simulation [3].