A new Hetero-material Stepped Gate (HSG) SOI LDMOS for RF Power Amplifier Applications Radhakrishnan Sithanandam and M. Jagadesh Kumar, Senior Member, IEEE Department of Electrical Engineering Indian Institute of Technology Delhi New Delhi, India 110016 E-mail: radhakrishnansj@gmail.com; mamidala@ieee.org Abstract In this paper, we propose a new hetero-material stepped gate (HSG) SOI LDMOS in which the gate is divided into three sections - an n + gate sandwiched between two p + gates and the gate oxide thickness increases from source to drain. This new device structure improves the inversion layer charge density in the channel, results in uniform electric field distribution in the drift region and reduces the gate to drain capacitance. Using two-dimensional simulation, the HSG LDMOS is designed and compared with the conventional LDMOS. We demonstrate that the proposed device exhibits 28% improvement in breakdown voltage, 32% reduction in on-resistance, 13% improvement in transconductance, 9% reduction in gate to drain charge and 38% reduction in switching delay. HSG LDMOS may be effectively deployed in RF power amplifier applications. 1. Introduction Laterally double diffused metal oxide semiconductor (LDMOS) technology is one of the most attractive technologies deployed in RF power amplifier applications because of its ease in integration to standard CMOS technology, high input impedance at high drive current and thermal stability [1]. Especially, silicon on insulator (SOI) LDMOS is more attractive due to its inherent dielectric isolation, high frequency performance and reduced parasitics [2]. However, achieving enhancement in all performance parameters like breakdown voltage, on-resistance, transconductance, drive current, gate to drain charge and switching characteristics is still an active area of research due to its tradeoffs [3]. For example, when we increase the breakdown voltage of the LDMOS, on- resistance also increases [4]. Similarly, when gate oxide thickness is scaled down for improving transconductance, gate to drain charge increases and reliability of gate oxide becomes questionable [5]. Therefore, the motivation of this work is to explore structural changes in SOI LDMOS to improve the device parameters. In this paper, therefore, we propose a new hetero- material stepped gate (HSG) LDMOS to improve the breakdown voltage and transconductance, and reduce the on-resistance, gate-charge and switching delays. We demonstrate using two dimensional device simulations [6] that the hetero-material stepped gate results in significant improvement in all the above device parameters when compared with the conventional LDMOS. In section 2, the proposed device structure and its fabrication procedure are explained. In section 3, we explain the expected enhancements with the TCAD simulation results. 2. Device Structure and Proposed Fabrication Procedure The HSG LDMOS and the conventional LDMOS used for simulation are shown in Fig. 1. As shown in the figure, in the case of HSG LDMOS, there are three steps of gate oxide with thickness, 25 nm, 50 nm and 150 nm from source end to drift region end respectively. The first and third gates are made of p + poly while middle gate uses n + poly. The physical dimensions and doping profiles are same for the conventional and the proposed device except that in the case of the conventional device, we have used a single n + poly gate and the gate oxide is chosen to be 50 nm. The gate oxide thickness and gate work function (n + and p + poly) combination of the proposed device is chosen such that the threshold voltage is approximately same as the reference device. The physical and doping parameters are shown in Table 1. Conference Proceedings: 23rd VLSI Design - 9th Embedded Systems, January 2010. Copyright © 2010 IEEE. All rights Reserved.