Exploring the Novel Characteristics of Fully Depleted Dual-Material Gate (DMG) SOI MOSFET using Two-Dimensional Numerical Simulation Studies Anurag Chaudhry and M. Jagadesh Kumar* Electrical Engineering Department, Indian Institute of Technology Delhi *mamidala@ieee.org Abstract The novel features of a fully depleted (FD) dual-material gate (DMG) SOI MOSFET are explored theoretically and compared with those of a compatible SOI MOSFET. The two-dimensional (2-D) numerical simulation studies demonstrate the novel features as threshold voltage roll- up and simultaneous transconductance enhancement and suppression of short-channel effects (SCE’s) offered by the DMG SOI MOSFET. Moreover, these unique features can be controlled by engineering the workfunction and length of the gate material. This work illustrates the benefits of high performance DMG SOI MOS devices over their single material gate (SMG) counterparts and provides an incentive for their experimental exploration. 1. Introduction Driven by the need to realize higher-speed and higher-packing density MOS integrated circuits, the dimensions of MOSFET’s have continued to shrink according to the scaling law proposed by Dennard et al. [1]. However, with the reduction of channel length, increasing amount of effort is focused to circumvent the “undesirable” short-channel effects (SCE), which cause the dependence of device characteristics, such as threshold voltage, upon channel length. Thin-film SOI MOSFET’s offer superior electrical characteristics over bulk MOS devices such as reduced junction capacitances, increased channel mobility and excellent latch-up immunity [2]. However, to take advantage of the ameliorated SCEs in fully-depleted SOI, t Si must be considerably smaller than the source/drain junction depth (t Si 10-15 nm). Moreover, there exits a strong coupling through the buried oxide in thin-film devices consequently, very thin buried oxides (t b 100 nm) are needed which tradeoffs with junction capacitance considerations. Ushiki et al. [3], used tantalum gate to facilitate the adjustment of the threshold voltage of an SOI device. But, it does not improve the carrier transport efficiency. Moreover, in an FD SOI device an arbitrary metal gate with workfunction close to the band edges would require a high channel doping to meet the off- current specifications. Alternative gate structures such as double-gate (DG) [4] have been proposed to improve the SCE and transconductance of SOI devices. But, they involve complicated processing as for a double-gate transistor [5]. In 1999, Long et al. [6], proposed a new type of FET structure, dual-material gate (DMG) FET, employing “gate-material engineering” instead of “doping engineering” to improve both carrier transport efficiency and short-channel effects. In a DMG FET, two different materials with different workfunctions are laterally merged together. In a DMG FET, the work function of metal gate 1 (M1) is chosen greater than metal gate 2 (M2) i.e.,  M1 >  M2 for an n-channel MOSFET and vice- versa for a p-channel MOSFET. This introduces a potential step in the channel. Thus the DMG structure achieves simultaneous suppression of short-channel effects and transconductance enhancement due to the creation of a step in the channel potential profile and a more uniform electric field distribution along the channel. With SOI rapidly emerging as the technology for next-generation VLSI the effects of DMG in sub-micron SOI technology remain to be investigated. In this paper, for the first time we have investigated the efficacy of DMG structure in FD SOI devices using 2-D numerical simulations. The unique features of the DMG SOI device are explored and compared with those of a SMG SOI in terms of threshold voltage (V th ) roll-off, drain-induced barrier lowering (DIBL), and the ratio of transconductance to drain conductance (g m /g d ) with a purpose of uncovering the potential benefits by their possible integration in current VLSI technology. 2. DMG-SOI Structure and Its Parameters A schematic cross-sectional view of a fully depleted DMG SOI MOSFET implemented in the 2-D device simulator MEDICI [7] is shown in Figure 1 with gate metals M1 and M2 of lengths L 1 and L 2 , respectively. The doping in the p type body and n + source/drain regions is kept at 6 x 10 16 cm -3 and 5 x 10 19 cm -3 respectively.