Low-power system-on-chip architecture for wireless LANs L. Bisdounis, C. Dre, S. Blionas, D. Metafas, A. Tatsaki, F. Ieromnimon, E. Macii, P. Rouzet, R. Zafalon and L. Benini Abstract: The authors present the architecture of a low-power system-on-chip (SoC) that implements baseband processing as well as the medium access control and data link control functionalities of a 5 GHz wireless system. The design is based on the HIPERLAN/2 wireless LAN standard, but it also covers critical processing requirements of the IEEE 802.11a standard. The options, constraints and motivations for the taken design decisions are presented, and the followed design steps, starting from the system specifications up to the architecture definition and the system implementation, are explained. The system’s functionality covers both mobile terminal and access point devices. A critical design task in such systems is the assignment of the target system’s tasks on the different types of processing elements available. Processor cores, dedicated hardware as well as memory elements and advanced bus architectures are used in order to achieve the target implementation. The architecture is targeted for a low-power SoC platform, due to the fact that power consumption is a critical parameter in electronic portable system design where excess power dissipation can lead to expensive and less reliable systems. A system prototype has been developed on a FPGA-based platform (including microprocessor modules). This FPGA-based prototype is currently being migrated to a SoC, which requires that the treatment of important issues such as clock handling, synthesis, testability and debugging is addressed. 1 Introduction A significant increase in market growth rates and a rapidly evolving technology for the wireless office and home networking have created a significant opportunity for chip design houses and manufacturers to develop new products [1]. For many years, the use of wireless LANs has been limited to a very few specialised vertical applications. However, since the introduction of standards [2] such as the ETSI BRAN HIPERLAN/2 (high performance radio local area network type 2) [3, 4] and the IEEE 802.11a [5] for wireless LANs, the market is moving in a new direction, gaining even greater momentum. The number of chips sold worldwide in 2002 in order to satisfy this demand exceeded 14 million units, an almost 75% increase from the previous year [1]. By 2006 it has been estimated that over 60 million wireless LAN semiconductor components will be shipped [1]. Although, both aforementioned standards operate in the 5 GHz band and are based on orthogonal frequency division multiplexing (OFDM) technology, their system character- istics differ significantly, especially in synchronisation and upper protocol layers’ processing [6]. Wireless communication systems require the optimis- ation of different factors including real-time performance, area, power, flexibility and time-to-market [7]. In order to optimise the combination of the above factors, instruction- set processors, custom hardware blocks as well as low- power memory and bus interface synthesis and mapping techniques are applied, offering a good balance between flexibility and implementation efficiency [8, 9]. The evolving scenario has serious consequences for any system-on-chip (SoC) development to be used in wireless systems. The protocol processor (that is able to run both the HIPERLAN/2 and IEEE 802.11a medium access control/ data link control (MAC/DLC) processes) is included in the proposed SoC in contrast with previous 5 GHz WLAN ASIC implementations [10, 11] in which an external protocol processor must be used. Note, that this external protocol processor cannot be the host processor (e.g. in a notebook or a base station), but is an additional dedicated processor able to run such applications. The lower MAC and DLC processing requirements of both WLAN standards are such that a dedicated processor in close collaboration with the baseband modem hardware (full access, on-chip buses for high speed) is needed for the real-time operation of the system. Additional advantages of the proposed architecture over the previous ones include: (i) the adopted low-power design methodology; (ii) the flexibility created by using an embedded CPU core for controlling the baseband modem and implementing the lower MAC processing of the q IEE, 2004 IEE Proceedings online no. 20030978 doi: 10.1049/ip-cdt:20030978 L. Bisdounis, C. Dre, S. Blionas, D. Metafas, A. Tatsaki and F. Ieromnimon are with INTRACOM S.A., Technical Division, 19.5 Km Markopoulo Ave., P.O. Box 68, GR-19002 Peania, Athens, Greece E. Macii is with the Dipartimento di Automatica e Informatica, Politecnico di Torino, Corso Duca degli Abruzzi 24, I-10129 Torino, Italy P. Rouzet is with STMicroelectronics, Advanced System Technology, Broadband Wireless LAN Group, Chemin du Champ des Filles 39, CH-1228 Plan-les-Quates-Geneve, Switzerland R. Zafalon is with STMicroelectronics, Advanced System Technology, Low-Power System Design Group, Via C. Olivetti 2, I-20041 Agrate Brianza, Milano, Italy L. Benini is with the Dipartimento di Elettronica Informatica e Sistemistica, Universita ´ di Bologna, Viale Risorgimento 2, I-40136 Bologna, Italy Paper first received 12th June and in revised form 3rd September 2003 2 IEE Proc.-Comput. Digit. Tech., Vol. 151, No. 1, January 2004