WSEAS TRANSACTIONS on CIRCUITS and SYSTEMS Nebi Caka, Milaim Zabeli, Myzafere Limani, Qamil Kabashi Manuscript received Dec. 20, 2006; revised March. 19, 2007 ISSN: 1109-2734 Issue 3, Volume 6, March 2007 281 Influence of MOFSET parameters in its parasitic capacitance and their impact in digital circuits NEBI CAKA, MILAIM ZABELI, MYZAFERE LIMANI, QAMIL KABASHI Faculty of Electrical and Computer Engineering University of Prishtina 10110 Prishtina, Fakulteti Teknik, Kodra e Diellit, p.n. KOSOVA nebi.caka@fiek.uni-pr.edu Abstract: Advanced development of technological processes influenced a wide use of MOSFET transistors in design of integrated digital circuits with high density packages (VLSI). However, in MOSFET transistors parasitic capacitances are present, which will influence on speed of operation in the circuits and dynamic dissipation power. The aim of this paper is to review the influence of channel dimensions, dimensions of source regions, dimensions of drain regions, concentration of impurity (doping concentration) in substrate, concentration of impurity in drain regions (source regions), concentration of impurity sidewalls, level of bias voltage values in particular parasitic capacitance values. Based on the results achieved actions will be determined in order to minimize parasitic capacitance that result in higher speed of operation and lower dynamic power dissipation. Decrease of region dimensions mentioned above depends on technological process capacity for minimal dimensions. Key words: MOSFET parameters, Parasitic capacitances, Gate capacitive effect, Junction capacitances, Speed of operation, Worst case conditions, Threshold voltage, Propagation delay, Concentration of impurity, Dynamic power dissipation. 1 Introduction When we analyze MOSFET in its transitive work regime (AC) we should have in mind the parasitic capacitances which influence the speed of operation of the MOSFET device and the MOSFET digital circuits. Considering the MOSFET’s structure, these capacitances are distributed and their exact calculation is quite complex. But, by using simple approximation, we can obtain the value of parasitic capacitances which can be used for analyzing the main characteristics of MOSFETs in AC. The Fig. 1 shows the cross-section view and the top view (mask view) of typical n-channel MOSFET (enhancement- type). Because the gate (L M ) has an extension over the source and drain regions (see Fig. 1), indicated with L D , the effective channel length is [1, 4, 5]: L = L M – 2L D (1) Note that the source and drain overlap region lengths are usually equal to each other because of the symmetry of the MOSFET structure. Typical values of L D are from 0.05L to 0.1L. Drain and source typical diffusion regions have a width denoted with W, length is denoted by Y and depth is denoted with x j . Both drain and source regions are surrounded by p + in three sides with the purpose of preventing the formation of any unwanted channels between two neighboring n + diffusion regions, i.e. to ensure that the surface between two such regions cannot be inverted (as in the case of integrated circuits). Based on physical structure of MOSFET, its parasitic capacitances can be classified into two major groups: – the gate capacitive effect (indicated by C ox ) and – junction capacitances drain-body and source-body. These two capacitive effects can be modeled by including capacitances in the MOSFET model between its four terminals, G, D, S, and B as shown in Fig. 2. There will be five capacitances: C gs , C gd , C gb , C sb and C db where the subscripts indicate the terminals [2, 3, 5, 6].