Low Power and Robust 8T/10T Subthreshold SRAM Cells Behzad Ebrahimi, Hassan Afzali-Kusha, and Ali Afzali-Kusha Nanoelectronics Center of Excellence, School of Electrical and Computer Engineering College of Engineering, University of Tehran, Tehran, Iran Abstract—In this paper, we propose a novel 8T subthreshold SRAM cell for improving the writing “0” characteristics of the conventional 8T cell. In addition, a new 10T subthreshold SRAM cell based on FinFET structures which has a lower standby power is suggested. The characteristics of the proposed and conventional 8T and 10T structures in 32 nm planar bulk and FinFET technologies are compared. The results show that the 10T structures have better write characteristics thanks to the differential write and consume less static power while the 8T structures have higher read currents. Also, they reveal that FinFET based structures show better read and write characteristics while consuming less static power with less variation in the presence of process variations. Keywords-subthreshold SRAM, 10T cell, 8T cell, FinFET, process variations, stability, low power. I. INTRODUCTION SRAM arrays occupy a large area of chips in the state of the art microprocessors and System on Chips (SOC) [1]. Its power dissipation could be one the important sources of power consumption. This limits the lifetime of portable devices such as implanted medical instruments and wireless sensor networks. To lower the power consumption of the arrays, one may lower V dd and operate the cells in subthreshold regime [2]. 6T SRAM cells based on planar bulk structures, however, have read stability problems in this regime due to the non-isolated read, short channel effects, and process variations [3]. New device structures and circuit topologies should be exploited to make subthreshold SRAM cells practical. Double gate transistors have a better control of short channel effects and immunity to the process variations. This is due to its thin film structure, extra gate, and also lightly doped body [4]. One type of double gate structures is FinFET [5] which is the most promising device to replace the planar bulk structure due to the similarity of its process to that of the planar bulk structure. In these devices, the gates on either side of the fin can be tied together or electrically isolated to allow an independent biasing scheme. This is achieved by selectively removing the gate material in the region directly on top of the fin. In the tied-gates mode (see Fig. 1(a)), the two gates are biased together to switch the FinFET ON/OFF [6]. In the independent-gates mode (shown in Fig. 1(b)), they are biased independently in a way that one gate is used to switch the FinFET ON/OFF and the other gate is used to adjust the threshold voltage. This feature can be utilized to improve the performance of the SRAM based on FinFETs [6]. Subthreshold 6T FinFET SRAM cells have been thoroughly investigated in [7]–[9]. Subthreshold SRAM cells implemented using 8T/10T transistors present more stability due to isolated read operation enabling further V dd reduction for planar bulk based structures [10][11]. 10T FinFET based subthreshold SRAMs have been studied in [3]. The study shows FinFET based cells have more stability and less power than their planar bulk counterparts. In the paper, we compare 8T and 10T subthreshold SRAM cells based on HSPICE simulations for 32 nm planar bulk and FinFET Predictive Technology Models (PTM) [12]. We also propose 8T design for both planar bulk and FinFET based structures to improve their write characteristic. In addition, we investigate utilizing independent-gates of FinFET for 10T structure to decrease its standby power. The rest of the paper is organized as follows. The structures of 8T and 10T subthreshold SRAM cells are described in Section II while SRAM characteristics for 32 nm planar bulk and FinFET technologies are compared in Section III. Finally, Section IV concludes the paper. II. 8T/10T SUBTHRESHOLD SRAM STRUCTURES The conventional 6T SRAM cell which is normally operated in the above threshold is shown in Fig. 2. The read butterfly plots for 6T SRAM cell for 32 nm technologies [12] are given in Fig. 3. (a) (b) Figure 1. Schematic of double-gate FinFET (a) tied-gates mode (b) independent-gates mode. Figure 2. Schematics of a conventional 6T SRAM cell. 2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 978-1-4673-0686-7/12/$31.00 ©2012 IEEE 141