A Dual-Mode Direct-Conversion CMOS Transceiver for Bluetooth and 802.11b Yeon-Jae Jung, Hoesam Jeong, Eunseok Song, Jungho Lee, Seung-Wook Lee * , Donghyeon Seo * , Inho Song * , Sanghun Jung * , Joonbae Park * , Deog-Kyoon Jeong, and Wonchan Kim Seoul National University, Seoul 151-742, Korea * GCT Semiconductor Inc., 2121 Ringwood Avenue San Jose CA 95131, USA Abstract A dual-mode direct-conversion transceiver integrates the transmitter of 0dBm output power and the receiver for both Bluetooth with -87dBm sensitivity and 802.11b with -86dBm sensitivity in a single chip with all building blocks shared for low cost and low power solution. Fabricated in 0.25μm CMOS process, die size is 8.4mm 2 including pads and current consumption in RX is 50mA for Bluetooth and 65mA for 802.11b. 1. Introduction As the need for a short-range wireless personal networking rapidly increases, numerous efforts has been focused on implementing a low power, low cost, and highly integrated RF IC, especially in the areas of Bluetooth (BT) and 802.11b. Since both two standards are targeted for the same 2.4GHz ISM band, a good deal of various building blocks of the two radios could be shared, in principle. Dual-mode transceivers [1-2], with the same motivation, have previously been proposed. However, these exploited the partial commonality partly due to different receiver architecture adoption in each mode. The proposed transceiver implements the dual-mode capability with a direct-conversion architecture for both modes and both transmit/receive (TX/RX) operations. Thus, a little area overhead is required since the transceiver can share baseband blocks as well as RF stages. Furthermore, since the two standards differ considerably in their bandwidth and dynamic characteristics, the power consumption of the dual-mode transceiver is optimized separately for each mode. The proposed dual-mode RF IC is a low power and low cost solution, which works in stand-alone with each commercial baseband chip and even does simultaneous operation of Bluetooth and 802.11b with a dual-mode baseband chip. 2. Architecture Fig. 1 shows the block diagram of the dual-mode transceiver. A direct-conversion architecture includes RF receive and transmit sections, clock generation, filtering, and linear amplification. In RX path, the single-ended low-noise amplifier first amplifies the received signal with high/low gain settings [3]. Then, the amplified signal is directly down-converted to the baseband with 2.4GHz LO signals. The baseband signal is first amplified by a high-linear, low-noise dual- ~ ~ ~ ~ ~ ~ DC-offset Cancellation PGA PGA PGA PGA Dual-mode Filter VCO PFD PRE- SCALER LOOP FILTER Serial Interface & Registers Channel Setting Reference Clock CLK GEN. DOU- BLER Filter Tuning Dual-mode PGAs LNA PA PGA PGA ~ ~ ~ ~ ~ ~ POLY- PHASE ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ DC-offset Cancellation PGA PGA PGA PGA PGA Dual-mode Filter VCO PFD PRE- SCALER LOOP FILTER Serial Interface & Registers Channel Setting Reference Clock CLK GEN. DOU- BLER DOU- BLER Filter Tuning Dual-mode PGAs LNA PA PGA PGA ~ ~ ~ ~ ~ ~ POLY- PHASE Fig. 1. Dual-mode transceiver architecture mode programmable gain amplifier (PGA) in order to mitigate the low noise requirement of the succeeding filter stage. Rejection of out-of-channel interferers is done by an active low-pass dual-mode filter, which is implemented by a Butterworth filter of 6 th -order. Then, three cascaded PGA stages provide sufficient gain to accommodate the signal range required by the A/D converters in the baseband IC. DC-offset caused by various sources is removed by the DC-offset cancellation block coupled with PGAs. In TX path, the transmitter takes the analog I/Q inputs from the baseband IC. The transmit spectrum shaping is performed by the TX filter. The following PGA linearly controls the amplitudes of the filtered I/Q signal in order to guarantee the TX mixer against the dynamic range loss. The TX baseband signal is directly up-converted to 2.4GHz by a single-sideband mixer and then, delivered to 50Ω load by the pre-amplifier (PA) with a nominal power level of 0dBm and 18dB gain control, achieved by the gain control in PGA and PA. A 1.2GHz fractional-N frequency synthesizer is used for the generation of the LO signal at half the desired frequency. Since the raster frequency is as small as 20kHz, the industry standard reference crystal oscillators can be used. The fractional-N synthesizer offers low in- band rms phase error due to wide loop bandwidth of 200kHz. The possible low frequency spur is suppressed by using the charge-averaging charge pump scheme [4].