Communication software synthesis from UML-ESL models Thiago Cardoso * , Edna Barros * , Bruno Prado *† and Andr´ e Aziz *‡ * Centro de Inform´ atica, Universidade Federal de Pernambuco, Pernambuco, Brazil † Departamento de Computac ¸˜ ao, Universidade Federal de Sergipe, Sergipe, Brazil ‡ Departamento de Estat´ ıstica e Inform´ atica, Universidade Federal Rural de Pernambuco, Pernambuco, Brazil e-mail: tfc@cin.ufpe.br Abstract—The electronic devices market demands a larger amount of functionality integrated into a single product. To address this demand, the industry migrated to solutions based on processors, increasing the software role in the systems. However, processor-based solutions raises the design complexity due to the complexity of Hardware-dependent Software (HdS). To cope with this complexity, the virtual platforms approach is applied, in which the whole system is modeled in order to reduce the design time. Nowadays, much of this work is manually performed, synthesizing all structures and behavior required in a system level design language (SLDL). However, with the increasing systems complexity, it is becoming impractical to continue performing this synthesis manually. In the last decade, several studies have addressed the synthesis of software components from descriptions in SLDLs and recently in the Unified Modeling Language (UML). Although significant automation has been obtained, there are limitations in the abstraction achieved. In order to raise the abstraction of the description, the UML-ESL profile was pro- posed to abstract the communication structure, with a synthesis technique for communication between software and hardware interfaces. This work presents a technique to synthesize the multitasking support and the communication between software components of the system from a description in UML-ESL for virtual platform simulation. The results obtained showed up to 60% decrease in the amount of code manually written. Index Terms—software synthesis, UML, ESL, platform-based design, virtual platforms, scheduling I. I NTRODUCTION The electronic devices market demands a larger amount of functionality integrated into a single product. To address this demand, the industry migrated to solutions based on pro- cessors, increasing the software role in the systems, reaching about 80% of the total of implemented components [1]. How- ever, processor-based solutions raises the design complexity due to the complexity of Hardware-dependent Software (HdS) that controls the hardware and software interface. To cope with this complexity, the virtual platforms approach is applied, in which the whole system (processor, devices, etc) is modeled in order to reduce the design time. This high level model allows the development of the software without the real hardware implementation, providing an early verification of the system. It is generated by mapping an application model to a platform model, through the synthesis of its hardware and software components. In order to achieve significative gains in productivity, this generation must be highly automated, but in JY ERW R3 R5 R4 R3 R4 Uejgfwnkpi Gzvgtpcn Eqoowpkecvkqp Kpvgtpcn Eqoowpkecvkqp Crrnkecvkqp eqfg JfU Fig. 1. Software synthesis example most systems the software component synthesis is performed manually. The software synthesis (Figure 1) comprises the application code generation and the HdS code generation. The former transforms the application model into sequential code in a target language for each software component in the system. The latter generates code that handles multitasking, the com- munication among software components (internal communi- cation) and the communication between a software and a hardware component (external communication). The challenge in automating the software synthesis is in the latter activity, whose complexity raises with the abstraction level of the application model, especially concerning the communication description, as it represents most of the HdS generation. In the last decade several studies have addressed the syn- thesis of software components from descriptions in system level design languages (SLDL). The SLDLs, such as SystemC and SpecC, model the communication aspects in the message level, following the taxonomy proposed in [2]. In this level the structure of the communication still must be modeled as interconnection among the modules of the system. It is possible to abstract these structural details by raising to the service level, where the communication is modeled in terms of function calls among the modules. Recently, established languages in the software engineer- ing field, such as the Unified Modeling Language (UML), have been used in automated synthesis approaches, but in most of them UML is used as a visual representation of a SLDL. Although significant automation has been obtained in these approaches, there are limitations in the abstraction level 978-1-4673-2608-7/12/$31.00 ©2012 IEEE