1 Quantum realization of some quaternary circuits Md. Mahmud Muntakim Khan, Ayan Kumar Biswas, Shuvro Chowdhury, Mehbuba Tanzid, Kazi Mohammad Mohsin, Masud Hasan and Asif Islam Khan δ Abstract—We present the design of quaternary quantum ver- sion of reversible circuits such as Toffoli gate, modified Fredkin gate, mux, demux, encoder-decoder using linear ion realizable quaternary Muthukrishnan-Stroud gates. Our realization of quaternary Toffoli gate is more efficient than the previous realization and other quaternary circuits are realized for the time in literature. Index Terms—Quantum computing, quaternary logic, Muthukrishnan-Stroud gate, Toffoli gate, Fredkin gate, mux, demux, encoder, decoder, Feynman gate. I. I NTRODUCTION While binary logic is the most usual/tradiational basis for quantum computation (QC) [1], multivalued logic offers several advantages for QC over their binary counterpart, such as better security for quantum cryptography [2], [3], more powerful quantum information processing [4], logarithmic reduction in the number of separate quantum systems needed to span the quantum memory [5]. Muthukrishnan et al. [5] showed that arbitrary unitary operations on any number of d-level systems (d> 2) or qudits can be decomposed into elementary logic gates that operate on only two systems or qudits at a time and these gates are experimentally realizable in linear ion trap scheme [6] of QC. We denote these two qudit elementary gates as Muthukrishnan-Stroud or M-S gates. Of late, there have been considerable interest in multiple valued, especially ternary quantum logic synthesis [10]–[14]. However, quantum ternary logic has the limitation that conventional binary logic functions cannot be very easily represented using the ternary base and the developed methods are applicable only for logic functions expressed in ternary base. A very promising alternative is quaternary logic, using which, besides quaternary logic functions, binary logic functions can be expressed by grouping 2-bits together into quaternary values. This sort of encoded realization of binary logic functions will theoretically reduce the total volume of the physical devices needed to approximately 1/log 2 4=1/2 times the original volume of the devices needed for binary case. Khan et al. [15] has recently provided a framework based on quaternary Galois field (GF(4)) for synthesizing quaternary quantum logic circuits. Quantum logic circuits are M. M. M. Khan, A. K. Biswas, S. Chowdhury, M. Tanzid, K. M. Mohsin are with the Department of Electrical and Electronic Engineering, Bangladesh University of Engineering and Technology, Dhaka 1000, Bangladesh. A. I. Khan was with the Department of Electrical and Electronic Engi- neering, Bangladesh University of Engineering and Technology, Dhaka 1000, Bangladesh. He is currently a graduate student at the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720, USA. ( δ e-mail: asif@eecs.berkeley.edu.) M. Hasan is with the Department of Computer Science and Engineer- ing, Bangladesh University of Engineering and Technology, Dhaka 1000, Bangladesh.(e-mail: masudhasan@cse.buet.ac.bd.) necessary for constructing oracles for implementing quantum algorithms [1] and quantum realization of ternary version of circuits such as Toffoli gate, half and full adder, parallel adder/subtractor, modified Fredkin gate, mux-demux etc. have been reported in literature [11], [12], [14] using linear ion trap realizable M-S gates. Khan et al. [15] presented the realization of only quaternary quantum Toffoli gate and quantum quaternary version of all the other circuits are yet to be reported in literature. In this paper, we present the quaternary quantum version of reversible circuits such as Toffoli gate, modified Fredkin gate, MUX-DEMUX, encoder- decoder on top of linear ion realizable Muthukrishnan-Stroud gates. II. QUATERNARY GALOIS FIELD ARITHMETIC Quaternary Galois field [QGF or GF4] is an algebraic structure that consists of the set of elements Q = {0, 1, 2, 3} and two binary operations addition (denoted by +) and multiplication (denoted by · or × or absence of any operator) as defined in Table I and II and satisfies the following axioms [15]: (A1) Associative law: a +(b + c)=(a + b)+ c. (A2) Commutative law: a + b = b + a. (A3)a +0= afor all a. (A4) For any a, there is an element (−a) such that a +(−a)=0 [For GF4, a = −a for all a]. (M1) Associative law: a · (b · c)=(a · b) · c. (M2) Commutative law: a · b = b · a. (M3) a · 1= a for all a. (M4) For any a =0, there is an element a -1 such that a · a -1 =1 [For GF4, 1 -1 = 1, 2 -1 = 3, 3 -1 = 2]. (D) Distributive law: a · (b + c)=(a · b)+(a · c). In this paper, we used +1, +2, +3 and 2×,3× operations to design the circuits. TABLE I GF(4) ADDITION + 0 1 2 3 0 0 1 2 3 1 1 0 3 2 2 2 3 0 1 3 3 2 1 0 Authorized licensed use limited to: Bangladesh Univ of Engineering and Tech. Downloaded on October 26, 2009 at 02:33 from IEEE Xplore. Restrictions apply.