THE COMPLEXITIES OF TODAY ’ S sys- tems on chips (SOCs) are outpacing the ca- pabilities of design tools and methodologies, resulting in long, expensive design and ver- ification cycles. One way to reduce this com- plexity is to rapidly compose these systems with predesigned, pretested functional cores available in VHDL libraries. 1 Thus, SOCs con- sist of a few cores that represent complex functions such as filters, sorters, and other primitives. Users can then store these cores in an application- and organization-specific reuse library (see box). Figure 1 on p. 44 illustrates the generic ar- chitecture of an SOC. System designers ob- tain cores in hard (implemented in a particular technology) or soft (register-trans- fer-level) format from vendors (often called intellectual property vendors). Cores are in- tegrated via a custom or commercial inter- connection network with a controller and a timing and function interface to the external world. Cores can be either new or legacy cores—inherited from existing designs. If the cores come from independent sources, inte- gration and test can be difficult, possibly re- quiring redesign of the cores to fit a common interface protocol. System designers synthe- size the controller during the design cycle ac- cording to customer requirements. Both decentralized and centralized controller ar- chitectures have appeared in the literature. The conventional core-based design ap- proach (box) is only one part (below the dotted line) of the holistic SOC design methodology shown in Figure 2. The holis- tic methodology begins with the tasks of cap- turing requirements, converting them to specifications, and ensuring that the cores meet these specifications both in their be- havior and their interaction protocols. (Thus, the early design tasks are concerned with what the SOC should do, while the lat- er stages are concerned with how it should be done.) These custom protocols often lead to communication problems and poor uti- lization. Therefore, the steps of protocol and architecture design, verification, and re- finement are very important. Performance modeling then ensures that the system meets required latency and throughput require- ments. Only after completion of these steps can we use conventional core-based design effectively. Library-based design raises new prob- lems. Designers must fully understand how to specify core-based systems at higher lev- els of abstraction. To correctly specify an ex- isting component from a reuse library, they must properly describe its functional, tem- poral, and interface properties. By “proper- ly,” we mean that the chosen specification should be precise and machine-processable. The specification can be either formal or in- Interface Design for Core-Based Systems I N TERFA CE D ESI G N 42 0740-7475/97/$10.00 © 1997 IEEE IEEE DESIGN & TEST OF COM PUTERS The authors propose the use of temporal abstraction in system-on- chip design and describe its benefits vis-à-vis traditional approaches. Their approach allows rapid integration of legacy cores to meet high-level system requirements. VIJAY K. MADISETTI Georgia Institute of Technology VP Technologies LAN SHEN Georgia Institute of Technology .