Design and implementation of 64 bit CMOS DRAM Memory Array and Peripheral Circuits Ayoush Johari School of Interdisciplinary Science and Technology International Institute of Information Technology, Pune ayoush.johari@gmail.com Abstract- Memory design is one of the interesting subjects in semiconductor technology. They have fascinated world through storage of data values and program instructions. Memory is a portion of a system for storing binary data in large quantities. Type of memory unit that is preferable or a given technology is governed by its architecture and other essential building blocks. Cell structure and topology is governed by the technology (Here 300 nm, 2 metal layer C5 process). The proposed memory design takes into account the type of memory unit that is preferable for a given technology and application and is a function of the required memory size, the time it takes to access the memory data, other access patterns and configuration to optimize the memory architecture for low power design and more importantly over all system requirements. The project is dealt with basic memory architecture and their essential peripheral blocks. The peripheral blocks include the address decoders, sense amplifiers, voltage references, drivers, buffers, timing and control. In this design we will be defining our memory size in bits (that are equivalent to the number of cells.) The proposed size of the array is 64 bits i.e. 8 x 8 array. Moreover this CMOS memory design will also be including sensing amplifiers and circuits, row and column decoders, control circuitry and finally the operation of memory cells themselves. Initially memory design procedure will be primarily consisting of defining the architecture and then laying out respective memory cell. Then according to architecture the peripheral circuitry is laid out. Finally memory check and optimization procedures are carried out with various simulation tools. Various schematics and Layouts are drawn and simultaneous comparisons are carried out using Electric CAD tool and basic simulations were carried out with LT Spice . Keywords—Semiconductor Memory, DRAM, Cell, Array, Spice, layout, Sense amplifiers, Decoder, Bitlines, Wordlines. I. INTRODUCTION The semiconductor industry is trying to catch up with Moore’s law by scaling the devices namely microprocessors and memories. Reduction in size guarantees reduction of its parasitic mainly capacitance. The parasitic mainly contribute to increment of size and unnecessary power dissipation in the overall device as a well designed layout of chip ensures quality of work and better performance. Fig.1. Semiconductor memory architecture and building blocks[6] Memories are circuits or systems that store digital information in large quantity [10]. This paper is on the analysis and design of CMOS Memories namely DRAM and associated peripheral circuits. Today memory circuits come in the form of SRAM, DRAM, ROM, EPROM, E2ROM, Flash and FRAM. Each of them has different cell designs, their basic structure, and organization and access mechanisms. Semiconductor memory is classified on the basis of functionality, access patterns and nature of storage mechanism. There are numerous number of aspects in memory design namely memory cells, memory arrays, peripheral circuitry, sense amplifiers, storage density and overall reliability. II. SEMICONDUCTOR MEMORY REALIZATION Semiconductor memories consists of storage elements arranged in a certain manner called arrays that are either flip- flops or capacitors. Fig.2. General design procedure for semiconductor memory