On Modeling Cross-Talk Faults Sujit T Zachariah, Yi-Shing Chang, Sandip Kundu, Chandra Tirumurti Intel Corporation, 3600 Juliette Lane, Santa Clara, CA 95052, USA Contact: Sandip.Kundu@intel.com Abstract Circuit marginality failures in high performance VLSI circuits are projected to increase due to shrink- ing process geometries and high frequency design techniques. Capacitive cross coupling between inter- connects is known to be a prime contributor to such failures. In this paper, we present novel techniques to model and prioritize capacitive cross-talk faults. Experimental results are provided to show effective- ness of the proposed modeling technique on industrial circuits. 1. Introduction In high performance designs, ensuring signal integrity has as- sumed an importance comparable to timing closure. Aggressive circuit designs such as domino pipeline, self-resetting circuits and cascode pass-transistor logic attain performance at the expense of reduced tolerance to noise. Settling for less than full potential of silicon performance is not an option in today’s highly competitive market place. This eliminates the choice of falling back to overly conservative circuit design practices to solve signal integrity problems. Cutting-edge designers must confront signal integrity problems head on without compromis- ing on performance. Noise has traditionally been treated purely as a design prob- lem. However, non-design issues such as time-to-market factors have prevented complete debug and resolution of all noise violations during the design phase itself. In today’s market place, a design may be fabricated in multiple fabrication sites and may be shrunk optically to take advantage of incremental progress in process technology. Even worse, it could be oper- ated at a slightly lower voltage as a low power part or at a slightly higher voltage as a high performance part. Given this market reality, it is neither possible to guarantee that a part will not suffer from signal integrity issues across the entire spectrum of process changes and supply voltage envelope nor is it wise to hold back a design for complete verification. However, even with the time-to-market constraints, the outgoing product quality still needs to be maintained and this has forced a significant change in the testing strategy of VLSI circuits. Conventional testing of VLSI circuits has focused on manufacturing defects, but the above mentioned design trends have resulted in novel testing strategies for failures resulting from noise and circuit marginality issues. Any phenomenon that causes the voltage of a circuit node that forms the connection between channel-connected components to deviate from its steady state logic value constitutes a source of noise. Often, a minor process change or supply voltage change can trigger signal integrity violations. The following sources of noise in digital circuits are the most critical from the perspectives of frequency of occurrence and severity of magni- tude. 0.25μm technology M3 M2 M2 0.89 0.48 0.45 0.77 0.25μm technology M3 M2 M2 0.89 0.48 0.45 0.77 0.5μm technology M3 M2 M2 0.98 0.75 0.95 0.75 0.5μm technology M3 M2 M2 0.98 0.75 0.95 0.75 Figure 1 Wire aspect scaling with technology.  Capacitive cross-talk noise results from parasitic coupling between adjacent signal nets and is most seen in nets that have weaker drivers than their adjacent peers [2]. With traditional scaling [16], transistors gain in performance and interconnects become more resistive. To mitigate this effect, interconnects are scaled differently in horizontal and vertical dimensions, resulting in dense lateral packing with larger capacitive expo- sure to adjacent nets (see Figure 1) [9]. With technology scal- ing, the noise magnitude increases as the drivers of the cou- pled nets switch faster. At the same time, the traditional toler- ance to noise is eroded by the reduction in supply voltage. The combination of these factors results in glitches and signal de- lays.  Power supply noise results from difference in voltage refer- ence levels between a local driver and receiver. The receiver may view this difference as input signal noise. This may result in extra signal transition delay or a catastrophic failure. Differ- 1530-1591/03 $17.00  2003 IEEE