06-1 Fast System-Level Prototyping of Power-Aware Dynamic Memory Managers for Embedded Systems David Atienza * , Stylianos Mamagkakis † , Marc Leeman ‡ , Francky Catthoor ‡§ , Jose M. Mendias * , Dimitrios Soudris † , Geert Deconinck §* DACYA/UCM, Avda. Complutense s/n, 28040 Madrid, Spain. Email: {datienza, mendias}@dacya.ucm.es † VLSI Design and Testing Center-Demokritus University, Thrace, 67100 Xanthi, Greece. Email: smamagka@ee.duth.gr § ESAT/K.U. Leuven, Kasteelpark A. 10, B3001 Heverlee, Belgium. Email: {name.surname}@esat.kuleuven.ac.be ‡ IMEC vzw, Kapeldreef 75, 3001 Heverlee, Belgium. Email: {name.surname}@imec.be Abstract— The rapid evolution in sub-micron process technol- ogy allows presently more complex systems to be implemented in embedded devices. In the near future, portable consumer devices must run multimedia and wireless network applications that require an enormous computational performance (1-40GOP S) at a low energy consumption (0.1-2W ). In these multimedia and wireless network applications, the dynamic memory subsystem is currently one of the main sources of power consumption and its inattentive management can severely affect the perfor- mance and power consumption of the whole system. Within this context, the construction and system-level power evaluation of custom dynamic memory managers is one of the most important and difficult parts for an efficient mapping of such dynamic applications on low-power and high-speed embedded systems. Moreover, they are subjected to design-time constraints due to market competition. As a result, current design technologies fall behind these requirements and consistent high-level design methodologies able to handle such complexity and enabling a short time-to-market are in great need. In this paper, we present a new system-level approach to model complex custom dynamic memory managers integrating a detailed power profiling method. This approach enables the developer to obtain power consumption estimates, memory usage and memory access values to refine the dynamic memory management of the system in a very early stage of the design flow and to explore the large search space of dynamic memory manager implementations without a time-consuming programming effort. I. I NTRODUCTION Over the last decade, the design gap between the top line digital signal processors (DSPs) and general-purpose processors has decreased. The innovations introduced in DSPs designed exclusively for performance are now implemented on DSPs targeted for hand-held devices where power con- sumption is a crucial design priority, both at the hardware and software design side. In the past, most implementations that were ported to these embedded platforms stayed mainly in the classic domain of signal processing and actively avoided algorithms that employ dynamic memory. Recently, with the emerging market of new portable devices that integrate multiple services such as multimedia and wireless network communications, the need to efficiently use dynamic memory in embedded low-power systems has arisen. Multimedia and wireless network applications have lately experienced a very fast growth in their variety, complexity and functionality. New applications (e.g. MPEG4 algorithms, 3D video applications or new network protocols) are now mixed signal and control dominated. These algorithms depend, with few exceptions, on dynamic memory for their operations due to the inherent unpredictability of the input data, which heavily influences global performance and memory usage of the sys- tem. Designing them for the (static) worst case memory usage would lead to a too high overhead in both memory footprint and power. Also, power consumption has become a real issue in overall system design (both embedded and general-purpose) due to circuit reliability and packaging costs [27]. As a result, optimization in general (and especially for embedded systems) has three goals that cannot be seen independently: memory usage, power consumptions and performance. Since the dynamic memory subsystem heavily influences performance and is a very important source of power con- sumption and memory usage, flexible system-level evaluation mechanisms for these three factors must be available at an early stage of the design flow for embedded systems. Un- fortunately, general approaches that integrate all of them do not exist presently at this level of abstraction for the dynamic memory managers involved. Many general dynamic memory management policies and implementations of them are nowadays available to pro- vide relatively good performance and low fragmentation for general-purpose systems [29], [7]. However, for embedded systems, such managers must be implemented inside their constrained operating system and thus have to take into account the limited resources available to minimize power consumption and preserve a certain level of performance. Thus, recent embedded operating systems (e.g. [15]) must use custom dynamic memory managers according to the underlying memory hierarchy and the kind of applications that will run on them. When custom dynamic memory managers are used, their implementations are manually optimized by the developer, typically considering only a limited number of implementa- tion alternatives, which are defined by the experience and inspiration of the developer. This limited exploration is mainly restricted due to the available time to implement and manually profile them. The construction and profiling of new custom implementations of dynamic memory managers and strategies has been proved to be programming intensive (and very time-consuming) since these managers are most of the times