IJMIE Volume 3, Issue 8 ISSN: 2249-0558 __________________________________________________________ A Monthly Double-Blind Peer Reviewed Refereed Open Access International e-Journal - Included in the International Serial Directories Indexed & Listed at: Ulrich's Periodicals Directory ©, U.S.A., Open J-Gage as well as in Cabell’s Directories of Publishing Opportunities, U.S.A. International Journal of Management, IT and Engineering http://www.ijmra.us 506 August 2013 DESIGN OF MODULO 2 n +1 FIR FILTER ARCHITECTURE Mrs.M. Thiruveni  D.Shanthi  Abstract —Filtering is one of the main operations in signal processing. The efficiency of the filter mainly depends on multiplier and adder. The modulo 2 n + 1 multiplier and adder are used to design modulo 2 n + 1 FIR filter architecture which is useful in applications like Residue Number System, Digital Signal Processing applications and cryptographic algorithms. In this multiplier [1], one operand uses weighted representation and another operand use diminished-1 representation. The new multiplier reduces the number of partial products which in turn reduces the operational time and power. Modulo 2 n + 1 adder [2] can produce modulo sums within the range {0, 2 n }, which is more than the range {0, 2 n − 1} produced by existing diminished-1 modulo 2 n + 1 adders. Since both units are designed effectively, the proposed FIR filter will be efficient. Keywords— FIR filter, dimnished-1 representation, residue number system, modular arithmetic, modular multiplier.  Associate Professor, Department of ECE, PSNA college of Engineering and Technology, Dindigul, Tamilnadu, India  Professor, Department of CSE, PSNA college of Engineering and Technology, Dindigul, Tamilnadu, India