1 A Fast Methodology for First-Time-Correct Design of PLLs using Nonlinear Phase-Domain VCO Macromodels Prashant Goyal Indian Institute of Technology, Kanpur, India Xiaolue Lai, Jaijeet Roychowdhury University of Minnesota, Twin Cities, USA Abstract— We present a novel methodology suitable for fast, correct design of modern PLLs. The central feature of the methodology is its use of accurate, nonlinear behavioral models for the VCO within the PLL, thus removing the need for many time-consuming SPICE-level simulations during the design process. We apply the new methodology to design a novel injection-aided PLL that acquires lock 3× faster than prior designs, without trading off other design metrics such as jitter. We demonstrate how existing design methodologies based on behavioral simulation are incapable of leading to our new PLL design. The nonlinear behavioral simulations employed in our methodology are about 2 orders of magnitude faster than transistor- level ones, resulting in an overall design productivity gain of an order of magnitude. I. I NTRODUCTION Phase locked loops or PLLs are important in virtually all mixed- signal and digital systems. For example, PLL synthesizers are em- ployed frequently in mobile communications and wireless commu- nication transceivers. In high-speed data communications systems such as Ethernet transceivers, disk drive read/write channels, digital mobile receivers, high-speed memory interfaces and so forth, PLLs are widely used as clock generators. Other uses include clock and data recovery (CDR) direct FM-demodulation in RF systems (see, eg., [1]). The design of PLLs constitutes one of the most challenging problems in mixed-signal design today. Because of complex nonlinear dynamics in their transient operation, achieving the right balance between various PLL design metrics — such as settling time, phase noise or jitter performance, lock and capture ranges, etc.— for a given application is far from simple. It is not uncommon, therefore, for many months to be required to finalize the design of today’s advanced PLLs. Employing effective design methodologies, supported heavily by simulation at different abstraction levels, is crucial in PLL design. Unfortunately, existing methodologies for PLL design are often inefficient or ineffective, with the result that it is not uncommon for 5 or more re-spins to be required before the PLL functions correctly. In existing methodologies, a fresh PLL design often starts from a simple first-principles block structure such as that shown in Figure 1, or from an existing PLL design. Rough hand calculations, based on simple classical linearized analysis of a PLL feedback loop in lock, are first performed by the designer to estimate lock range, jitter, etc.. During the course of the design, behavioral simulation using phase-domain macromodels is extensively applied for greater accuracy. When the design is finalized at the transistor level, full SPICE-level simulation is heavily used for final verification. Important steps in this flow break down in today’s methodologies. It is for this reason that, as mentioned above, PLL design tends to be extremely time consuming and error prone. Problems exist at each level of the above flow that contribute to the breakdown: • hand calculation level: Existing hand-analysis techniques [1], [2] for dynamics, noise, jitter, etc., in PLLs are all based on linear analysis of the PLL around a locked steady state. The few nonlinear analyses that are amenable to hand calculation (eg., for estimating lock range [3]) are overly simplistic for most practical designs; for example, they do not take dynamics, which are very important in determining PLL responses, into account. Therefore, the rˆ ole of simulation in PLL design assumes much greater importance than for the design of simpler systems like op-amps. • system-level simulation with behavioral models (or macromodels): Behavioral simulation using phase-domain macromodels is extremely important in PLL design [4], [5] because of the great speedups it offers over transistor-level full simulation. Existing behavioral simulation of PLLs relies largely on using linear models for most components, especially for the VCO phase macromodel. The main issue with VCO behavioral models is unacceptable loss of accuracy and predictive power. Although it has generally been assumed that linear VCO macromodels 1 [4], [6] are adequate for behavioral simulation of PLLs, it has recently been demonstrated that using them can lead to very serious prediction errors [7], especially in the presence of nonlinear transient effects such as those involved in the capture, lock acquisition, and slipping processes in PLLs. The predictive power of linear VCO models is particularly poor for advanced PLL designs that use feed-forward or injection-aided mechanisms to enhance performance [8]–[10], as we investigate in detail in this paper. (Section III explains these mechanisms and design techniques in more detail.) • transistor-level circuit simulation: In view of the significant accuracy problems in hand- and behavioral-level analysis of PLLs, designers rely heavily on transistor-level circuit simulation in existing PLL design methodologies. Such full simulation has the great advantage that it is able to predict non-ideal and nonlinear effects accurately. Unfortunately, as practitioners are well aware, full simulation of PLLs is extraordinarily time consuming. For example, a single jitter simulation for an industrial PLL can take days. The reason for the inefficiency of full SPICE-level simulation of PLLs stems from the fact that loop dynamics are typically orders of magnitude slower than the oscillation frequency of the VCO, resulting in a classic fast/slow timescale situation, where very small simulation time-steps need to be taken over a very long total simulation period. Because the only option for accurate PLL simulation in today’s methodologies is so slow, designers are often forced to ignore large parts of the design space or to skip important verification steps simply due to time pressure. It is mainly for this reason that PLL design tends to be particularly error prone. In this paper, we present a fast, accurate and extremely effective methodology for designing any kind of PLL. Our methodology involves extensive use of behavioral simulation using nonlinear VCO phase-domain macromodels that are automatically generated via algorithm from transistor-level VCO circuits. Our use of nonlinear phase macromodels is motivated by recent work [7], [11] which has established their suitability for predicting a variety of advanced or non-ideal effects, such as injection locking, capture and acquisition transients, jitter due to power supply variations, etc.. The most im- portant benefit of the proposed methodology is that it dispenses with the need for time-consuming transistor-level simulations to a much greater extent than previously possible. The nonlinear behavioral 1 ie., the VCO inside the PLL is modeled as a linear integrator [6].