International Journal of Electrical & Computer Sciences IJECS-IJENS Vol:09 No:09 14 1916091-IJECS-IJENS © October 2009 IJENS I J E N S FPGA Based Implementation of Baseline JPEG Decoder Jahanzeb Ahmad, Mansoor Ebrahim Faculty of Engineering, Sciences and Technology, IQRA University, Karachi Pakistan. jahanzeb.ahmad@iqra.edu.pk , mansoorebrahim99@hotmail.com Abstract--The JPEG standard (ISO/ IEC 10918-1 ITU-T Recommendation T.81) defines compression techniques for image data. As a consequence, it allows to store and transfer image data with considerably reduced demand for storage space and bandwidth. From the four processes provided in the JPEG standard, only one, the baseline process is widely used. In this paper FPGA based High speed, low complexity and low memory implementation of JPEG decoder is presented. The pipeline implementation of the system, allow decompressing multiple image blocks simultaneously. The hardware decoder is designed to operate at 100MHz on Altera Cyclon II or Xilinx Spartan 3E FPGA or equivalent. The decoder is capable of decoding Baseline JPEG color and gray images. Decoder is also capable of downscaling the image by 8. The decoder is designed to meet industrial needs. JFIF, DCF and EXIF standers are implemented in the design. I. INTRODUCTION Communication and storage cost are reduced by doing data compression. Data compression techniques can be divided into two categories “losy” and “lossless”. Lossless compression model are based on entropy coding schemes. This model is widely used for text and data compression. In lossless compression model exact data is obtained at the receiver. Lossy compression model produces close approximation of the original data at the receiver. Video, Image and audio compression commonly use lossy compression Compression ratio up to 100:1 can be achieved depending on the fidelity of the data. There are several standards/formats for image compression/ decompression. Joint Photographic Experts Group (JPEG) [1, 17], Graphics Interchange Format (GIF) [7 8], Portable Network Graphics (PNG) [9], JPEG 2000 [10], Tagged Image File Format (TIFF) [11]. JPEG is a very well know image compression standard. It is widely adopted as compression standard for still images. Joint Photographic Expert Group (JPEG) is a joint workgroup of three international standard organizations, International Organization for Standardization (ISO), International Telegraph and telephone consultative committee (CCITT) and International Electrotechnical commission (IEC). Enormous amount of data storage is required for digital images/video. An uncompressed color image requires 24 bits for each picture element (pixel). A 6 Mega pixel (3038 X 2012) camera requires 17.5 Mega Bytes, when stored uncompressed, same image when compressed with JPEG take almost 1.7 Mega bytes depending on the compression ratio. En-hui Yang, Longji Wang [18] proposed an algorithm which can further improve this ratio, the algorithm is iterative, which is more complex to implement in Hardware. Digital devices are now more popular then analog devices especially in the field of multimedia (Audio, Video and Image) because of amazing improvement in digital signal processing algorithms and fast hardware. Digital storage media is more reliable and less effected by noise and distortion. Real-time implementation of JPEG encoder or decoder requires efficient and fast hardware architecture. So architecture specific implementation is required to achieve real-time results. Variety of architecture designs capable of supporting real time image/video processing already exists such as ASIC, FPGA, Microprocessor and Digital signal processor based design, which implements different algorithms for image and video processing. But only a few efficient architectures are implemented for Image and video compression, decompression, processing [12, 13, 14, 15, 16, 19, 20, 21, 22, 23, 32]. Shizhen Huang and Tianyi Zheng [12] proposed an architecture for PNG image decoding, they used combination hardware and software approach which reduce the throughput of the system. Zulkalnain MohdYousof, et al. [13] proposed a Digital Signal processor based JPEG Decoder but it can only support small resolution images. R. P. Jacobi et al. [14] proposed an FPGA based JPEG decoder design but its maximum operating frequency is 38.7 MHz on Vertex 6 which is very slow for commercial design. Mario kovac and N. Ranganathan [15] presented encoder architecture which is capable of operating at 100 MHz and can support 1024x1024 spatial color image resolution. Mohammed Elbadri et al [16] also proposed a FPGA based design for JPEG decoder this design also has low operating frequency, 67 MHz. Kyeong- Yuk Min and Jong-Wha Chong [19] proposed an architecture for JPEG Encoder. Zulkalnain MohdYusof et al [20], proposed a Digital Signal Processor (DSP) based architecture, DSP based systems have low development time and cost but low throughput as compare to FPGA. FPGA is relatively young technology. FPGA can provide speed, performance and flexibility because parallel and