B.Vijayapriya et al Int. Journal of Engineering Research and Applications www.ijera.com ISSN : 2248-9622, Vol. 3, Issue 6, Nov-Dec 2013, pp.972-976 www.ijera.com 972 | Page Design of Low Power Novel Viterbi Decoder Using Transmission Gates B.Vijayapriya, Dr.S. Padma, Prof.B.M.Prabhu, PG scholar Angel college of engineering andtechnology,Tirupur Assistant Professor Angel college of engineering andtechnology,Tirupur Professor Sona College of Technology Salem Abstract In this paper a low power viterbi decoder based on transmission gates is presented.In wireless communication, Viterbi decoder which consumes more power plays an important role in communication applications. Viterbi decoder is used to decode the received data which is encoded using convolutioncodes. In this paper in order to reduce the power consumption and to improve the performance of the decoder optimized transmission gate logic is proposed. As the multiplexer and flip flops are the major parts in the viterbi decodercircuit, transmission gate is used to reduce the complexity of the circuit. The proposed technique is simulated using tanner tool. The simulated result shows the power consumption of viterbi decoder using TG is lower compared toCMOSlogic and also the number of transistors required to design the Viterbi decoder is reduced using TG logic. Keywords: Viterbi decoder, transmissiongates, tanner tool I. Introduction Viterbidecoder is based on viterbialgorithmwhich was proposed by Viterbi in 1967.The algorithm is mainly used to decode the convolutioncodes in digital communication systems. Theviterbi algorithm(VA) provides the most accurate way to find maximum likelihood sequence of transmitted signal. In order to transmit the analog signal through the digital communication system, the signal should be sampled and quantized before proceeding through the system. In this paper, it is assumed that the digital values are transmitted through channel. The Viterbi algorithm is used to find the signals which are corrupted by noise in the channel. Theviterbi decoder consists of three major blocks such as branch metric unit, add compare and select unit and survivor memory unit. The Viterbi algorithm is based on treills diagram and the encoder circuit is considered as a finite state machine. In order to find out the errors in the received sequence the hamming distance of that sequence is calculated. Viterbi decoders are widely used in wireless communication specifically it is widely used in third generation mobile terminals and the decoder circuit consumes more power in the transmission system In presentscenario reducing the power consumed by a device is a major factor in VLSI technology. Even though the CMOS logic design plays a major role in designing devices with low power consumption, the switching activity of the CMOS devices causes more power consumption. For low power consumption, different logic styles may be used. In this paper, the design based on transmission gate is proposed for low power consumption application. II. Proposed Design The proposed method is based on transmission gates.The transmission gate(TG) circuitis given in the figure 1. Figure1.A simple transmission gate Transmission gate(TG) which consist of one n-MOSFET and one p-MOSFET acts as a switch where the NMOS passes strong ‘0’ and the PMOS passes strong ‘1’.The transmission gate logic is often used for the design of multiplexers and Exclusive OR gates. Since the multiplexers and EXOR gates are the major blocks in many digital systems, the number of transistors and the power consumed is reduced by using TG logic. III. Design of viterbi decoder using TG The Viterbi decoder consists of three major blocks such as Branch metric unit, Add compare and select unit and Survivor memory unit. In this chapter the blocks of viterbi decoder are explained using transmission gates. RESEARCH ARTICLE OPEN ACCESS