An advanced Method for Synthesizing TLM2-based Interfaces Nadereh Hatami, and Zainalabedin Navabi Electrical and Computer Engineering School, University of Tehran {nhatami, Navabi}@cad.ut.ac.ir Abstract Transaction Level Modeling (TLM) describes system on chips at a high abstraction level in which simulation is faster than the traditional design flow. TLM2 serves the designer with three distinct coding styles among which the untimed style has the best simulation speed with the lowest accuracy. In this paper, we are presenting a method of synthesizing TLM untimed descriptions directly to synthesizable behavioral description from which they can be converted to RTL. This direct mapping skips the intermediate synthesis steps and speed up the design process. We restrict our proposed method to TLM interfaces and specifically work on DMA devices as a common interface in communications sharing a common bus between a processor and its I/O devices. 1. Introduction Transaction Level Modeling (TLM) approaches are proposed to describe Systems-On-Chips at a higher abstraction level than RTL. [2, 3, 4] describe TLM as a high level transaction language based on SystemC. TLM simulates faster than RTL, even for complex systems, allows embedded software validation and integration testing to be done earlier in the design. A possible approach to Transaction-Level Modeling is to create a single model to fit all purposes: embedded software development, performance evaluation, etc. In such a model, transactions have to correspond directly to the operations performed on interconnect, whose size is the bus width. Timings details as well as arbitration are also present. However, this approach does not cope well with conflicting requirements from the various TLM activities [4]. The alternative solution is to take advantage of blocking interfaces which is independent of the interconnect bus width and timing details. It simulates faster, with the expense of loss of details. As the design proceeds in the design flow, this abstract model should be replaced with a more detailed architecture of what is really going to be done. This detailed architecture can then be synthesized to RTL. Some works are done on TLM synthesis to extract RTL model of the design from the transaction level description. [5] is a high-level solution that integrates electronic system level designs with block-level implementation. [6] also uses a library of synthesizable TLM protocols to synthesize transaction level descriptions into SystemC RTL code. In this paper, we are going to focus on interfaces as a means of communication in TLM designs, and among all interfaces we focus our attention on DMA as the architecture that allows data to be sent directly from an attached device (such as a disk drive) to the memory. The idea lies behind the fact that with recognizing familiar hardware structures in the design and mapping them to the synthesizable equivalence structure, we would speed up the synthesis process of the design. In the next section, after an overview of TL modeling in SystemC with respect to TLM2 untimed coding styles, we describe our methodology for TLM synthesis in Section 3. We survey the TLM2 untimed model design followed by the SystemC synthesizable equivalence and introduce a way to test the synthesizable design in the high abstraction level TLM2 structure. In Section 4, we explain the experimental results by considering the coding styles of high level and synthesizable design. Section 5 is the conclusion. 2. TLM2 untimed modeling TLM2 consists of a set of core interfaces, analysis ports, initiator and target sockets, and the generic payload. The core interfaces support untimed, loosely- timed and approximately-timed coding styles. Each coding style can support a range of abstraction across functionality, timing and communication. The generic payload supports the abstract modeling of memory- mapped buses, together with an extension mechanism to support the modeling of specific bus protocols whilst maximizing interoperability [1].