Hindawi Publishing Corporation VLSI Design Volume 2010, Article ID 230783, 13 pages doi:10.1155/2010/230783 Research Article Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations Kumar Yelamarthi 1 and Chien-In Henry Chen 2 1 School of Engineering and Technology, Central Michigan University, Mt Pleasant, MI 48859, USA 2 Department of Electrical Engineering, Wright State University, Dayton, OH 45435, USA Correspondence should be addressed to Kumar Yelamarthi, kumar.yelamarthi@cmich.edu Received 2 June 2009; Revised 19 October 2009; Accepted 3 December 2009 Academic Editor: Ethan Farquhar Copyright © 2010 K. Yelamarthi and C.-I. H. Chen. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. The complexity of timing optimization of high-performance circuits has been increasing rapidly in proportion to the shrinking CMOS device size and rising magnitude of process variations. Addressing these significant challenges, this paper presents a timing optimization algorithm for CMOS dynamic logic and a Path Oriented IN Time (POINT) optimization flow for mixed- static-dynamic CMOS logic, where a design is partitioned into static and dynamic circuits. Implemented on a 64-b adder and International Symposium on Circuits and Systems (ISCAS) benchmark circuits, the POINT optimization algorithm has shown an average improvement in delay by 38% and delay uncertainty from process variations by 35% in comparison with a state-of-the-art commercial optimization tool. 1. Introduction The performance improvement of microprocessors has been driven traditionally by dynamic logic and microarchitectural improvements [1] and can be further enhanced through circuit design and topology organization. Dynamic logic is an effective logic style in terms of timing and area when compared to its static counterpart due to (1) the absence of requirement for design implementation in complementary PMOS logic, and (2) the use of a clock signal in its implementation of combinational logic circuits. In general, CMOS dynamic logic uses fast NMOS transistors in its pull- down network. Its delay is dependent on the number and size (width) of transistors in the NMOS critical path. This paper presents an NMOS transistor sizing optimization for a faster operation. Static logic is slower because it has twice the loading, higher thresholds, and actually uses slow PMOS transistors for computation. Dynamic logic has been predominantly used in microprocessors, and their usage has increased the timing performance significantly over static CMOS circuits [1, 2]. However, timing optimization of dynamic logic is challenging due to several issues such as charge sharing, noise-immunity, leakage, and environmental and semicon- ductor process variations. Also, with dynamic circuits con- suming more power over static CMOS, an optimal balance of delay and power can be achieved at the architectural level through effective partitioning of design into a mixed-static- dynamic circuit style [3]. Process variations introduce design uncertainties at each step of process development, design, manufacturing, and test. The ratio of these process variations to the nominal values has been increasing with the shrinking device size towards 32 nm [4], causing an impending requirement to account for process variations during timing optimization. They need to be taken into account during the design phase to make sure that performance analysis provides an accurate estimation [5]. One of the challenges in timing optimization of CMOS logic is delay uncertainty (Δ) from process variations, Δ = T max − T min , where T max and T min are the maximum and minimum delays of a timing path. In the 180 nm CMOS