Available online at www.scholarsresearchlibrary.com Scholars Research Library Archives of Applied Science Research, 2013, 5 (3):278-282 (http://scholarsresearchlibrary.com/archive.html) ISSN 0975-508X CODEN (USA) AASRC9 278 Scholars Research Library Design a floating-point fused add-subtract unit using verilog Mayank Sharma, Aswani Sengar and Prince Nagar ECE Department, Sharda University, Gr. Noida, U.P., India ____________________________________________________________________________________________ ABSTRACT A floating –point fused add subtract unit is described that performs simultaneous floating –point add and subtract operations on a common Pair of single –precision data in about the same time That it takes to performs a single addition with a Conventional floating –point adder. Placed and routed in 45nm process. So that there will be less consumption of memory as well as power. ___________________________________________________________________________________________ INTRODUCTION Much research has been done on the floating-point fused multiply add (FMA) unit [1].It has several advantage in a floating-point unit design. Not only can a fused multiplier-add unit reduce the latency of an application that executes a multiplication followed by an addition, but the unit may entirely replace a floating point co-processor’s floating adder and floating-point multiplier. Many DSP algorithms have been rewritten to take advantage of the presence of FMA units in a given systems with FMA systems. For example, in [4] a radix-16 FFT algorithm is presented that speeds up FFTs in systems with FMA units. High-throughput and digital filter implementations are possible with the use of FMA unit. FMA units were utilized in embedded signal processing and graphics applications, used to perform division, argument reduction, and this is why the FMA started to become an integral unit of many commercial processors such as IBM, HP[7] and Intel [9]. Similar to operation performed by a FMA in many algorithms in DSP and other field both of the sum and difference of a pair of operands are needed for subsequent processing. For example, this is required in computation of the FFT & DCT butterfly operations. In traditional floating-point hardware these operations may be performed in a serial fashion which limits the throughput. The use of a fused adds subtract (FAS) unit accelerates the butterfly operation. Alternatively, the add and subtract may be performed in parallel with two independent floating point adders which is expensive. This paper investigate implementation of floating point add-subtract unit this paper investigates the implementation of a floating-point fused add-subtract unit shown in figure 1. It performs the following operations: