International Journal International Journal International Journal International Journal of of of of Signal Processing, Image Processing and Pattern Recognition Signal Processing, Image Processing and Pattern Recognition Signal Processing, Image Processing and Pattern Recognition Signal Processing, Image Processing and Pattern Recognition Vol. Vol. Vol. Vol. 6, No. , No. , No. , No. 2, , , , June June June June, 20 , 20 , 20 , 2013 13 13 13 1 Synchronous Sampling Rate Conversion using Frequency domain based techniques Chunduri SreenivasaRao 1 , A. AroakiaRaj 2 , Dhulipalla VenkataRao 3 1 Software Development Engineer, AMD India Pvt Ltd, Hyderabad, India. 2 Software Development Engineer, QualComm Pvt Ltd, Hyderabad, India. 3 Principal, Narsaraopet Institute of Technology, Guntur (Dist), A.P., India chsrinivas19800305@rediffmail.com, arock0405@gmail.com, dvenky221101@rediffmail.com Abstract Sampling rate conversion is, in general, implemented using time domain based poly-phase filter structures. The other way of implementing multi-rate signal processing is frequency domain based approach, which has the advantage of computational savings. This paper clearly explains how to apply frequency domain processing techniques for sampling rate conversion. The proposed approach is applied to both power of 2 and non-power of 2 sampling rate conversion factors. The properties of FFT are utilized analytically to solve the implementation problems such as non-power of 2 sampling rate factors. The theoretical computational complexity of the proposed approach is provided. The simulation results of proposed approach are compared with the quality of time domain approach and the comparison shows that differences are insignificant. Keywords: Complex FFT, Computational complexity, Decimation, Interpolation, Sampling Rate Conversion, Overlap save method. 1. Introduction In many practical applications of signal processing, it is desired to convert the sampling frequency of signals due to the variation in operating bandwidth of various systems. The conversion could be either increase or decrease in sampling frequency depending on the system requirement. Sampling rate conversion (SRC) can be achieved in two ways. The signal could be converted to analog signal at input sampling frequency and resampled using analog to digital conversion at the desired sampling rate. This method has some disadvantages in terms of quantization error and signal distortion that occur during analog to digital conversion and vice versa. The other way of achieving sampling rate conversion is using digital domain [1][2][3]. In synchronous SRC, there exists an integer relationship between input and output clock rates, whereas in asynchronous SRC, it is the fractional relationship. In decimation, the input signal is filtered at the desired sampling rate before applying decimation factor to avoid aliasing effects. In case of interpolation, zeros are inserted between two successive samples of input signal and then filtered to avoid the image noise. The number of zeros to be inserted depends on the interpolation factor. Typically this value will be interpolation factor minus one. [1][2][3]. For efficient implementation of sampling rate conversion, one usually prefers time domain based poly-phase filtering structures where the redundant MAC (Multiply and ACcumulate) operations are eliminated. In decimation process, only the selected samples based on decimation factor will be transmitted and hence filtering is required for the selected samples. In case of interpolation, the MAC operation result becomes vanish for