Nidhi Pokhriyal et al Int. Journal of Engineering Research and Applications www.ijera.com ISSN : 2248-9622, Vol. 3, Issue 6, Nov-Dec 2013, pp.1469-1472 www.ijera.com 1469 | Page Compressor Based Area-Efficient Low-Power 8x8 Vedic Multiplier Nidhi Pokhriyal 1 , Harsimranjit Kaur 1 , Dr. Neelam Rup Prakash 2 1 M.E. Research Scholar, E&EC Department, PEC University Of Technology, Chandigarh. 2 Supervisor and Head, E&EC Department, PEC University Of Technology, Chandigarh. Abstract Multipliers are the integral components in the design of many high performance FIR filters, image and digital signal processors. Multipliers being the most area and power consuming elements of a design, area-efficient low-power multiplier architectures are in demand. In this paper, multiplier based on ancient Vedic mathematics technique has been proposed which employs 4:3, 5:3, 6:3 and 7:3 compressors for addition of partial products. Combining the Vedic Sutra- Urdhwa Tiryakbhyam and efficient compressors, a robust area and power efficient multiplier architecture has been achieved. The designs were synthesized and analysed in Cadence RTL compiler in 180 nm technology. When compared with previous compressor based multiplier, the proposed design achieves 30.5% and 25.8% reduction in power and area respectively. Keywords: Vedic multiplier, Urdhwa Tiryakbhyam Sutra, compressor, low-power I. INTRODUCTION Multipliers are the key components of all the digital signal processors (DSPs), FIR filters and image processors and the performance of these processors is largely determined by the kind of multipliers used. They are generally the most area consuming and hence power consuming units in the design. Therefore, optimizing the area and power of the multiplier is a major design issue.. Several multipliers have been proposed and designed over past few decades [1]. In these algorithms, the multiplication process requires several intermediate stages to get the final result due to which critical path gets lengthened. Also, these intermediate stages require additional hardware which leads to increase in area and power consumption. To overcome these disadvantages, multipliers based on Vedic Mathematics technique have been proposed in [2] and [3] where all the partial products are obtained well in advance much before the actual operation of multiplication begins, which results in a high speed design. A compressor based multiplier has also been in proposed in [4] which utilises 4:2 and 7:2 compressors to reduce the intermediate stages. In this paper, novel multiplier architecture is proposed which can efficiently reduce the intermediate stages as compared to compressor based multiplier, by using high order compressors such as 4:3, 5:3, 6:3, 7:3 compressors [5] Section II describes Urdhwa Tiryakbhyam Sutra for 8-bit multiplication. Section III explains the high order compressors used in this paper. Section IV describes the proposed multiplier. Section V and Section VI discusses the comparative results and conclusions. II. VEDIC SUTRA - URDHWA TIRYAKBHYAM The 16 Vedic Sutras apply to and cover almost every branch of Mathematics. They apply even to complex problems involving a large number of mathematical operations. Among these sutras, Urdhwa Tiryakbhyam Sutra is the most efficient for performing multiplication. The use of this sutra can be extended to binary multiplication as well .This Sutra translates to “Vertical and crosswise”. It utilizes only logical AND operation, half adders and full adders to perform multiplication where the partial products are generated prior to actual multiplication. This saves a considerable amount of processing time. Moreover it is a robust method of multiplication. Consider two 8-bit numbers, a (a 8 -a 1 ) and b (b 8 -b 1 ) where 1 to 8 represents bits from the least significant bit to the most significant bit. The final product is represented by P (P 16 -P 1 ). In Fig.1, the step by step method of multiplication of two 8-bit numbers using Urdhwa Tiryakbhyam Sutra is illustrated. The bits of the multiplier and multiplicand are represented by dots and the two way arrow represents the logical AND operation between the bits which gives the partial product terms. In the conventional design of Urdhwa Tiryakbhyam sutra based multiplier, only full-adders and half-adders are used for addition of the partial products. But, the capability of full-adder is limited to addition of only 3 bits at a time. RESEARCH ARTICLE OPEN ACCESS