Abstract — Quantum-Dot Cellular Automata is a technology that is a feasible alternative to current CMOS technology based on transistors. In the future, CMOS device scaling results in leakage and short channel effects which make it unattractive for use. QCA (Quantum-Dot Cellular Automata) based circuits shrink the device size to Quantum levels and provide scope for further improvement and research. Majority Gates and Inverters mainly form the basic building blocks in QCA circuit design. The Three-input Majority Gate is most widely used in logic synthesis and design. In this paper, a Nine-input Majority Gate is proposed which would find use in multi-bit arithmetic circuits by reducing overall cell counts and delays. Further, the proposed design is simulated on QCA designer to prove its functionality and uses. Index Terms— Quantum-Dot Cellular Automata, Majority Gate, QCA logic I. INTRODUCTION Presently, all electronic circuits are made and fabricated using CMOS technology. Current CMOS circuits however, have serious issue when we scale the device size to quantum levels. Problems such as those of leakages, short channel effects, over-heating and signal attenuation are evident in all these cases. Keeping in mind the roadmap for development in electronics, it is believed that the device size would shrink to seven nm by 2019 [1]. At that stage, transistors will fail to function properly and thus QCA logic design becomes important. QCA cells consist of quantum dots in which electrons can reside. Information is conveyed to the cell based on the orientation of the electrons. Data flows from one cell to the other by electrostatic interactions. This type of information flow does not involve actual electron flow and thus results in a reduction in the overall power consumption of the circuit. This feature of QCA circuits enables their usage at very high frequencies such as in RF circuitry [2-5]. QCA cells conduct data from one to another and thus are simply used as wires. In digital QCA design, the side-effects of using metal contacts such as junction capacitances, parasitic capacitance and high latency delays are all eliminated. Existing QCA circuits are made using the simple Manuscript received January 22 nd , 2013. This work was supported in part by the Indian Institute of Technology Kanpur. Ankit Kumar is with the Indian Institute of Technology Kanpur 208016 India (e-mail: krankit@iitk.ac.in). Puneet Agrawal is with the Indian Institute of Technology Kanpur 208016 India (e-mail: agrawalp@iitk.ac.in). Dr. Bahniman Ghosh is a professor of Electrical Engineering at the Indian Institute of Technology Kanpur 208016 India (e-mail: bahniman@iitk.ac.in). blocks of the Majority Gate and the Inverter. Many papers have been previously published that describe the usage of QCA architecture in designing simple adders, multipliers, ALUs and microprocessors [4, 6-15]. Mainly, three input majority gates have been used to design digital circuits; however some papers have been published describing the use of five input majority gates. The usage of five input gates reduces the fabrication area and the complexity of the circuit. A Seven-input majority gate has also been proposed in literature [16]. Using this design, the paper proposes to further reduce the complexity and the cell count of the circuit, especially in multi-bit design. Using a Seven-input gate also allows us to create four input „AND‟ and „OR‟ gates. In this paper, a new design for a nine input majority gate is proposed. The simulations of the design are performed on QCA Designer. The proposed design is a single layer design and uses only a single clock, thus minimizing the information processing delay. II. QCA OVERVIEW A. Basics A QCA cell is a device that consists of four quantum wells. In each cell, two excess electrons reside in two of these wells. Based on the principle of the minimization of the total system potential energy, the electrons always take up the diagonally opposite positions at all times. Thus, two binary states in which the cell can reside can be used to describe the information contained in the cell. One position of the two electrons describes a „1‟ and the other state describes a „0‟ for showing the two potential levels in normal present-day digital design as shown in Fig. 1. Figure 1. The two electronic states for any QCA cell. III. CLOCKING IN QCA TECHNOLOGY QCA circuits have a four phase clock unlike CMOS circuits where there are only two states „high‟ and „low‟. All the four phases in QCA clocking have a phase shift of 90˚, as shown in Fig. 2. Power to the QCA circuit comes in the form of clock itself unlike external power supply as is the case in CMOS style. The four phases of clock correspond to „switch‟, „hold‟, „release‟, and „relax‟ [17, 18, 19, 20]. In „switch‟ phase, the barriers are slowly raised and the QCA cells become polarized according to the state of their input drivers. In the next „hold‟ phase, the barriers are kept high so that the A Novel Nine Input Majority Gate Design in Quantum-Dot Cellular Automata Ankit Kumar, Puneet Agrawal and Bahniman Ghosh Indian Institute of Technology Kanpur