SYSTEMC MODELING FOR 3D GRAPHICS HARDWARE ACCELERATION Tse-Chen Yeh, Ruei-Ting Gu, Hung-Yu Chen and Ing-Jer Huang Department of Computer Science and Engineering National Sun Yat-Sen University Kaohsiung, Taiwan ABSTRACT Due to the growing complexity of system architecture current today, the system modeling is utilized in the early design under the time-to-market. To establish a 3D graphics acceleration platform, we need to explore the system architecture and performance issues. In this paper, we use SystemC to model our hardware models including accelerator, SDRAM memory, and graphics engine (GE) for investigating hardware and software implementations. And the experimental results give the open issues of performance tuning and architecture exploration on 3D graphics acceleration on embedded system. 1. INTRODUCTION 3D graphics applications become popular on mobile devices and other embedded systems. To build the system consists of the HW/SW co-development, and the time-to-market is critical in the conventional design flow. RTL simulation slow down the hardware development and the software utility must to wait the usable hardware prototype. On the stage of system integration, we will face the performance tuning and architecture adaptation, however, it is impossible for porting huge software using RTL simulation. Our goal is to apply 3D graphics on digital television (DTV) system in real time. In order to establish the acceleration platform in time, we use system modeling to speedup the simulation time and explore the performance issues of whole system. On the other hand, the abstraction level which we called TLM (Transaction Level Model) can reduce the simulation time by omitting the model details of hardware implementation. We choose SystemC for modeling language and the CoWare TM Platform Architect for the analysis toolkit on performance tuning. The organization of this paper is as follows. In Section 2, the related works are presented, which includes the SystemC modeling and basic knowledge on 3D graphics pipeline. The specification analysis is described in Section3. In Section 4, we present the modeling flow and implementation details. And we compare the hardware and software simulation results in Section 5. Finally, the future works and open issues for our research are summarized in Section 6. 2. RELATED WORKS 2.1 System modeling using SystemC SystemC dominates the properties of language on system modeling. In practice, SystemC created into the form of class library in C++, it can be integrated with software function block as simulation. The kernel of SystemC is a process scheduler to handle the concurrency mechanism which is the significant feature of hardware behaviour [1][2]. TLM is the medium layer on hardware modeling, which higher than register transfer level (RTL), but lower than algorithmic level, the classifications of TLM are presented by [3]. By omitting the pin-accurate details, TLM economizes large simulation time which separate hardware model into computation and communication. S. Pasricha et al. extended the TLM approach to model a SoC platform for architecture exploration [4]. In terms of Platform Architect utilizes the model library for the platform building based on ARM cores, the library consist of Embedded Processor Model (EPM) and Transactional Bus Simulator (TBS) [5-6]. The EPM embedded the ARM instruction set simulator (ISS) for run-time software simulation. Besides, the TBS is built into a hierarchical channel with arbitration module and address decoder. Inside the TBS also contain the analysis library which can record the transaction information for bus performance analysis. 2.2 3D graphics pipeline OpenGL ES specification provided by the Khronos Group specifies the 3D graphics pipeline implemented on embedded system which shows in Fig. 1 [7]. This spec. defines the order of primitive processing and API which interfaces between the users and OS/driver. Fig. 1: 3D graphics pipeline in OpenGL ES 1.1