Logic Design Considerations for 0.5-Volt CMOS K. Joseph Hass Jack Venbrux Prakash Bhatia NASA Institute of Advanced Microelectronics University of New Mexico jhass@mrc.unm.edu jvenbrux@mrc.unm.edu pbhatia@mrc.unm.edu Abstract As the operating supply voltage for commercial CMOS devices falls below 2V, research activ- ities are underway to develop CMOS integrated circuits that can operate at supply voltages well under 1V. Although dramatic power reductions can be achieved using low supply voltages in high performance applications, the increased subthreshold leakage that results when transistor threshold voltages are lowered can render some conventional logic circuit styles unusable. Fur- thermore, some low voltage circuits are not robust when faced with normal variations in threshold voltage. This paper examines the design considerations for logic and memory circuits in very low voltage CMOS, and compares simulated behavior with measurements of fabricated test circuits. These circuit examples were chosen because they illustrate the unique design challenges of low voltage CMOS. 1. Introduction Driven by the need to reduce power consumption and maintain high reliability in leading edge integrated circuits, the nominal operating supply voltage for these devices is falling steadily [3– 6, 9]. In order to maintain high switching speed at low supply voltages it is necessary to reduce the transistor threshold voltage, V T , in proportion. For supply voltages much below 1 V the value of V T may be just tens or hundreds of millivolts, and the subthreshold leakage current of these transistors becomes significant [2]. However, the power savings achieved by operating at low voltages can be much larger than the power lost to increased static current. The total average power consumption of a CMOS circuit can be expressed as P TOTAL P STATIC P DYNAMIC if we focus on these two primary components. To first order, P STATIC is proportional to V DD and P DYNAMIC is proportional to V 2 DD C LOAD F CLOCK , where V DD is the supply voltage, C LOAD is the average capacitance that must be switched in each clock cycle, and F CLOCK is the operating clock frequency. Because of the V 2 DD nature of dynamic power, dramatic gains in overall power consumption can be made by reducing the supply voltage. If we simultaneously decrease V T to maintain performance then the static power component will increase, but not as quickly as dynamic power decreases. The minimum average power operating point for any circuit occurs when the supply voltage is reduced to the point that the dynamic power and static power components are roughly equal. However, there are additional engineering challenges that appear when attempting to use tran- sistors with very small V T values [8]. The normal variation of V T during manufacturing, and with This research was supported by NASA under Space Engineering Research Grants NAG5-8392 and NAG5-7360.