On the Fundamental Design Gap in Terabit per Second Packet Switching M. Verhappen IBM Research, Zurich Research Laboratory S¨ aumerstrasse 4 8803 R¨ uschlikon Switzerland mav@zurich.ibm.com P.H.A. van der Putten, J.P.M. Voeten Eindhoven University of Technology Electrical Engineering, ICS/CND P.O. Box 513, 5600MB Eindhoven, Netherlands p.h.a.v.d.putten, j.p.m.voeten @tue.nl Abstract We discuss the gap we experience in an industrial de- sign path of high-speed packet switches. As bandwidth de- mand exceeds progress in CMOS technology, system archi- tects are forced to abandon familiar design solutions and make fundamental changes to their architectures at an in- creasingly faster pace. We investigate design methods to decrease the risk of such changes and to provide a struc- tured and confident transition from conceptual system-level models to hardware descriptions. It appears that the de- sign gap is caused by differences between language prim- itives and underlying concepts of system-level design lan- guages and hardware description languages. We substanti- ate the need for expressive system-level modeling concepts and show that the gap is actually caused by a fundamental interpretation mismatch between models and descriptions. Based on a comparison of existing system-level synthesis methods with the interpretation gap, we propose to decrease the gap by using modeling patterns. 1 Introduction We focus on design methods for research in the area of high-speed packet switches such as PRIZMA [12]. These modular switches target the high-end portion of the market with an aggregate throughput in excess of one terabit per second. Such high performance requirements can currently only be met if the system is built using the latest hardware technology. History shows that hardware integration density and ag- gregate bandwidth demand grow exponentially. However, the motivation for a more efficient design cycle is not so much only the growth rates of these areas per se, but rather the discrepancy between the different acceleration rates (Gilder’s versus Moore’s Law). Integration density has been the main motor of system scalability for many generations of high-speed packet switches. However, the currently pre- dicted progress in integration density cannot keep up with the growth of bandwidth demand. Additionally, other im- portant factors cannot keep up with bandwidth demand, namely physical system dimensions in general and inter- connection density and power per area in particular. Our experience shows that the differences between those growth rates force designers to develop new system concepts at an increasingly faster pace than before. The safe and relatively cheap incremental solutions over the past decade have to make room for fundamentally different approaches. This change entails risks because mature design knowledge of older packet-switch generations has become partly obso- lete. The new knowledge is initially empty and needs to be filled with new system-level concepts. Efficient system- level design methods are needed to fulfill that task in order to minimize the risk entailed by such fundamental changes. Examples [17][14] show that starting the specification and design of complex systems is best done using system- level design and formal specification languages such as LO- TOS (Language of Temporal Ordering Specifications), SDL (Specification and Description Language) or POOSL (Par- allel Object-Oriented Specification Language) [8][9][5]. Such languages provide a formal syntax and formal seman- tics for unambiguous specification and verification. The only way to manage growing complexity and make the right system-level trade-offs, is abstract modeling. In this fash- ion, we are able to create models to answer questions about new conceptual solutions instead of immediately describ- ing the entire system at a lower level of abstraction. In such models we apply abstraction to hide system aspects that are of lesser interest in the particular context of such questions. In principle, the powerful language primitives and underly- ing concepts of these languages and techniques can be used to facilitate this kind of modeling [14][16][18]. In the remainder of this paper we identify a gap in the design path from concept models to synthesizable hardware descriptions. It is our objective to decrease this gap so that