978-1-4244-9183-4/10/$26.00©2010IEEE 222 Performance Evaluation of High Speed Compressors for High Speed Multipliers Using 90nm Technology N. Ravi 1 , T. Jayachandra Prasad 2 , M. Umamahesh 3 RGM College of Engineering & Technology, JNT University, Anantapur, AP-518501, India. 1 ravi2728@gmail.com, 2 jp.talari@gmail.com, 3 mahesh_ mallavarapu@yahoo.co.in T. Subba Rao S. K. University, Anantapur, AP-515003, India. sushmasurekha@yahoo.com. Abstract—This paper describes high speed compressors for high speed parallel addition multipliers like Booth Multiplier, Wallace Tree Multiplier in Digital Signal Processing (DSP). We proposed 4- 3, 5-3, 6-3 and 7-3 compressors for high speed multiplication. The compressors reduce vertical critical path more rapidly than conventional compressors. A 5-3 conventional compressor can take four steps to reduce bits from 5 to 3, in the case of proposed it takes only 3 steps. All the compressors are designed with half adder and full Adders. These compressors are simulated with T-Spice at a temperature of 25 0 C with fixed frequency of 10MHz at 2.0V and 1.0Vwith 90nm MOSIS technology. The Power Delay Product (PDP) of these compressors calculated to analyze the delay and energy consumption. Keywords- Compressors; Adder; Delay; Power and PD; I. INTRODUCTION With the recent trend in increasing mobility and performance in small hand-held mobile communication and portable devices, among three areas i.e speed, area and power, speed has become one of the emphases in modern VLSI design. Parallel multipliers can be used to speed up the processors comparative serial multipliers. There are two basic approaches to enhance the speed of parallel multipliers, one is the Booth algorithm and the other is the Wallace tree compressors or counters. But as per as power concern these two methods are not suitable, energy dissipation will be more [1]. Multiplier architecture can be divided into three stages, a partial product generation stage, a partial product addition stage and final addition stage. Multipliers require high amount of power and delay during the partial products addition. For higher order multiplications, a huge number of adders or compressors are used to perform the partial product addition [2]. The number of adders was minimized by introducing different high order compressors. Binary counter property has been merged with the compressor property to develop high order compressors such as 5-3, 6-3 and 7-3 compressors [3-4]. II. WALLACE TREE In multipliers if speed is not an issue, the partial products can be added serially to reduce the design complexity. In high-speed designs say 16 bit [5], the Wallace tree method is usually used to add the partial products. In this method all the bits in each column at a time and compresses them into two or three bits. Adders and compressors can be used to vertical bits compression. An adder itself a compressor, it can compress three bits into two bits. Hence it is a 3-2 compressor. For high order multiplication, high order compressors can be used to compress the bits [6-7]. In [3], 16 * 16 bit multiplication, Fig1. 4 - 3, 5 – 3, 6 – 3 and 7 – 3 compressors are designed with half adders, full adders and a logic block is used in vertical compression of the bits. But in this paper the compressors are designed with complete efficient half adders and full adders which are discussed in later sections. Figure 1. 16 * 16 bit Wallace Tree multiplier III. A REVIEW ON ADDERS Half Adder: A half adder can be construct with one AND and one XOR gate. In this paper an efficient low power design is used to construct XOR gate [8].