INTERNATIONAL JOURNAL OF RESEARCH IN COMPUTER APPLICATIONS AND ROBOTICS www.ijrcar.in Vol.2 Issue.2, Pg.: 74-81 February 2014 R.Balakumaresan Page 74 INTERNATIONAL JOURNAL OF RESEARCH IN COMPUTER APPLICATIONS AND ROBOTICS ISSN 2320-7345 DESIGN OF FLIPFLOP FOR POWER REDUCTION USING CLOCK PAIRING TECHNIQUE R.Balakumaresan Assistant Professor Department of Electronics and Communication Engineering, PSNA of Engineering and Technology, Dindigul. Abstract— A large portion of the on chip power is consumed by the clock system which is made of the clock distribution network and flip-flops. So the objective is to reduce the power consumption. A method of “Conditional Data Mapping Flip Flop” (CDMFF) was proposed earlier. The drawbacks of CDMFF are it uses more number of transistors and it has a floating node on its critical path. Moreover it cannot be used in noise intensive environment. So we propose a method called “Clocked Pair Shared Implicit Pulsed Flip Flop” (CPSFF) here. In this method the number of transistors is reduced by sharing the clocked pair transistors. The design is implemented in MICROWIND 3.1. Analysis of the performance parameters shows that performance of CPSFF is superior compared to conventional flip flop. The overall power is reduced in CPSFF when compared to the previous method CDMFF.. Keywords: CDMFF, CPSFF, Power Delay Product. I. INTRODUCTION The System-On-Chip (SoC) design is integrating hundreds of millions of transistors on one chip, whereas packaging and cooling only have a limited ability to remove the excess heat. All of these results in power consumption being the bottleneck in achieving high performance and it is listed as one of the top three challenges in ITRS 2008. The clock system, which consists of the clock distribution network and sequential elements (flip-flops and latches), is one of the most power consuming components in a VLSI system. It accounts for 20% to 40% of the total power dissipation in a system. As a result, reducing the power consumed by flip-flops will have a deep impact on the total power consumed. A large portion of the on chip power is consumed by the clock drivers. Caution must be paid to reduce clock load when designing a clocking system. There is a wide selection of flip-flops in the literature. Many contemporary microprocessors selectively use master-slave and pulsed-triggered flip-flops. Traditional master-slave single-edge