282 IETE JOURNAL OF RESEARCH | VOL 55 | ISSUE 6 | NOV-DEC 2009 High Speed Vedic Multiplier for Digital Signal Processors Ramesh Pushpangadan, Vineeth Sukumaran, Rino Innocent, Dinesh Sasikumar, Vaisak Sundar Department of ECE, College of Engineering, Munnar, PB NO 45 County Hills, Idukki, Kerala, India ABSTRACT Digital signal processors (DSPs) are very important in various engineering disciplines. Fast muliplicaion is very important in DSPs for convoluion, Fourier transforms etc. A fast method for muliplicaion based on ancient Indian Vedic mathemaics is proposed in this paper. Among the various methods of muliplicaions in Vedic mathemaics, Urdhva iryakbhyam is discussed in detail. Urdhva iryakbhyam is a general muliplicaion formula applicable to all cases of muliplicaion. This algorithm is applied to digital arithmeic and muliplier architecture is formulated. This is a highly modular design in which smaller blocks can be used to build higher blocks. The coding is done in VHDL (very high speed integrated circuits hardware descripion language) and synthesis is done using Xilinx ISE series. The com- binaional delay obtained ater synthesis is compared with the performance of the modiied Booth Wallace muliplier which is a fast muliplier. This Vedic muliplier can bring about great improvement in DSP performance. Keywords: Muliplier, Urdhva iryakbhyam, Vedic mathemaics. 1. INTRODUCTION High speed arithmetic operations are very important in many signal processing applications. Speed of the digital signal processor (DSP) is largely determined by the speed of its multipliers. In fact the multipliers are the most important part of all digital signal processors; they are very important in realizing many important functions such as fast Fourier transforms and convolutions. Since a processor spends considerable amount of time in per- forming multiplication, an improvement in multiplication speed can greatly improve system performance. Multipli- cation can be implemented using many algorithms such as array, booth, carry save, and Wallace tree algorithms. The computational time required by the array multiplier is less because the partial products are computed independently in parallel. The delay associated with the array multiplier is the time taken by the signals to propagate through the gates that form the multiplication array [1]. Arrangement of adders is another way of improving multiplication speed. There are two methods for this: Carry save array (CSA) method and Wallace tree method. In the CSA method, bits are processed one by one to sup- ply a carry signal to an adder located at a one bit higher position. The CSA method has got its own limitations since the execution time depends on the number of bits of the multiplier. In the Wallace tree method, three bit signals are passed to a one bit full adder and the sum is supplied to the next stage full adder of the same bit and the carry output signal is passed to the next stage full adder of same number of bit and the then formed carry is supplied to the next stage of the full adder located at a one bit higher position. In this method, the circuit lay out is not easy [2]. Booth algorithm reduces the number of partial products. However, large booth arrays are required for high speed multiplication and exponential operations which in turn require large partial sum and partial carry registers. Multiplication of two n-bit operands using a radix-4 booth recording multiplier requires approximately n/ (2m) clock cycles to generate the least signiicant half of the inal product, where m is the number of booth recoded adder stages. Thus, a large propagation delay is associated with this case [1]. The modiied booth encoded Wallace tree multiplier uses modiied booth algorithm to reduce the partial products and also faster additions are performed using the Wallace tree. This paper proposes a novel fast multiplier adopting the sutra of ancient Indian Vedic mathematics called Urdhva tiryakbhyam [3]. The design of the multiplier is faster than existing multipliers reported previously. 2. FPGA ARCHITECTURE This section describes the Xilinx ield programmable logic arrays based on the architecture of Virtex-II. All Xilinx FPGA contain the same basic resources – slices (grouped into conigurable logic blocks), IOBs and programmable interconnect. The other resources [Downloaded free from http://www.jr.ietejournals.org on Friday, February 28, 2014, IP: 117.231.92.252] || Click here to download free Android application for this jou