IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 4, APRIL 2008 881 Exploring Variability and Performance in a Sub-200-mV Processor Scott Hanson, Member, IEEE, Bo Zhai, Mingoo Seok, Member, IEEE, Brian Cline, Kevin Zhou, Meghna Singhal, Michael Minuth, Javin Olson, Leyla Nazhandali, Todd Austin, Dennis Sylvester, Senior Member, IEEE, and David Blaauw, Member, IEEE Abstract—In this study, we explore the design of a subthreshold processor for use in ultra-low-energy sensor systems. We describe an 8-bit subthreshold processor that has been designed with en- ergy efficiency as the primary constraint. The processor, which is functional below 200 mV, consumes only 3.5 pJ/inst at 350 mV and, under a reverse body bias, draws only 11 nW at 160 mV. Process and temperature variations in sub- threshold circuits can cause dramatic fluctuations in performance and energy consumption and can lead to robustness problems. We investigate the use of body biasing to adapt to process and tem- perature variations. Test-chip measurements show that body bi- asing is particularly effective in subthreshold circuits and can elim- inate performance variations with minimal energy penalties. Re- duced performance is also problematic at low voltages, so we in- vestigate global and local techniques for improving performance while maintaining energy efficiency. Index Terms—Low voltage, process variation, sensor network processing, subthreshold. I. INTRODUCTION A S RESEARCH in ultra-low-power circuit design ad- vances, a vision of highly integrated mobile computing systems with lifetimes of the order of years is emerging. Such computing systems are attractive for biomedical implants, supply chain management, and environmental monitoring [1]. The energy consumption of these systems ultimately limits form factor, battery life, and complexity. It is therefore critical to develop circuits capable of performing complex tasks under stringent energy constraints. A number of low-power digital design techniques have been explored over the past several decades, but supply voltage scaling is generally shown to be the most effective technique due to the quadratic dependence of dynamic energy on the supply voltage . Recent research has shown that minimum energy is typically achieved when enters the subthreshold region [2], [3]. Subthreshold circuits have been shown to be functional below 200 mV [4] and with energy consumption of the order of picojoules per instruction [5]. Recent work has also explored the challenges of ultra-low-voltage memory design [6]–[10]. How- ever, a number of daunting challenges remain for subthreshold circuits. The most important concern is variability. Exponential Manuscript received August 26, 2007; revised November 2, 2007. S. Hanson, M. Seok, B. Cline, K. Zhou, M. Minuth, L. Nazhandali, T. Austin, D. Sylvester, and D. Blaauw are with the University of Michigan, Ann Arbor, MI 48109 USA (e-mail: hansons@umich.edu). B. Zhai is with Advanced Micro Devices, Austin, TX 78741 USA. M. Singhal and J. Olson are with Advanced Micro Devices, Boxborough MA 01719 USA. Digital Object Identifier 10.1109/JSSC.2008.917505 sensitivities to , and temperature make even small vari- ations problematic. Performance is also considerably degraded at low voltage since nodes are charged and discharged by weak inversion currents. The speeds of subthreshold digital circuits have typically been reported in the kHz and low-MHz ranges [4], [5]. To guarantee widespread adoption of subthreshold de- sign, it will be necessary to address both of these issues. In this study, we explore the subthreshold design space and address the variability and performance problems of low-voltage operation. We begin in Section II by describing an 8-bit processor that has been fabricated in a 0.13 m technology [13]. The architecture is described in detail with emphasis placed on accommodations made for energy effi- ciency. Measurements show that the processor is functional below 200 mV and that the total energy consumption is only 3.5 pJ/instruction at 350 mV. With the application of a reverse body bias, the power consumption goes as low as 11 nW. In Section III, we propose a body biasing strategy that takes advantage of the unique sensitivities of subthreshold operation. We contrast the body bias sensitivities of subthreshold circuits with those of super-threshold circuits . Measure- ments of the subthreshold processor show that robustness at low voltages can be improved dramatically with the application of a body bias and that performance fluctuations induced by process and temperature variability can be eliminated with minimal en- ergy penalties. In Section IV, we explore techniques for improving perfor- mance in the subthreshold processor. We first compare body bi- asing and voltage scaling for improving performance globally. We then discuss sizing techniques for improving performance locally. At low voltages, gate-length sizing can give an exponen- tial increase in drain current due to reverse short-channel effects (RSCE). Test-chip measurements show that gate-length sizing is superior to gate-width sizing for improving performance along timing critical paths. II. TEST-CHIP OVERVIEW A. Architecture While our energy efficiency improvements are primarily de- rived from aggressive voltage scaling, architectural decisions can have a dramatic impact on the energy efficiency of a system. We have accordingly adopted a simple-processor architecture but have made a number of additions to enhance energy ef- ficiency. A system-level diagram of the processor and CPU, 0018-9200/$25.00 © 2008 IEEE