High-Level Simulation of Substrate Noise in High-Ohmic Substrates with Interconnect and Supply Effects G. Van der Plas 1 , M. Badaroglu 1,2 , G. Vandersteen 1,3 , P. Dobrovolny 1 , P. Wambacq 1,3 , S. Donnay 1 , G. Gielen 4 , and H. De Man 1,4 1 IMEC, DESICS, Kapeldreef 75, B-3001 Leuven, Belgium, 2 also Ph.D. student at K.U. Leuven, Belgium, 3 also lecturer at Vrije Universiteit Brussel, Belgium, 4 ESAT, K.U. Leuven, Belgium Abstract Substrate noise is a major obstacle for mixed-signal integration. In this paper we propose a fast and accurate high-level methodology to simulate substrate noise generated by large digital circuits. The methodology can handle any substrate type, e.g. bulk-type or EPI-type, and takes into account the effects of interconnect and supply. For each standard cell a substrate macromodel is used in order to efficiently simulate the total system, which consists of a network of such macromodels. For a 40K gates telecom circuit fabricated in a 0.18 µm CMOS process, measurements indicate that substrate noise is simulated by using our methodology within 20% error but several orders of magnitude faster in CPU time than a full SPICE simulation. Categories and Subject Descriptors I.6.5 [Computing Methodologies]: SIMULATION AND MODELING – Model Development, Modeling methodologies. B.7.2 [Hardware]: INTEGRATED CIRCUITS – Design Aids, Simulation; Verification General Terms Design, Verification Keywords model order reduction, modeling, substrate noise 1. INTRODUCTION The integration of the digital and the analog circuits on the same die brings some difficulties that endanger the gains in performance and form factor. One of the most important problems is the parasitic supply coupling and substrate noise coupling, which is caused by the fast switching of the digital gates [1]. Methodologies that check at the same time generation, propagation and immunity of analog designs to the substrate noise, are not yet mature. Typically, this problem is studied after the layout, which is too late in the design flow. Very often, only the isolation efficiency is checked without usually knowing the amount of noise injected into the substrate. Previous work on gate-level characterization of substrate noise is very limited. For substrate noise the first effort to model gates with a lumped equivalent model has been made in [2] where a digital gate is modeled by a current source in parallel with its circuit and n-well capacitance. Methodologies that make use of real substrate noise waveforms extracted for each standard cell are presented in [3][4][5]. For every gate, a substrate noise current signature is extracted for every switching activity at the inputs. In [3][4], only switching at the outputs, which is coupled into the substrate via the drain capacitance, is taken into account, not at the inputs and the effects of the noisy power supply. We have presented a methodology named SWAN (S ubstrate W aveform AN alysis) [6][7], which accurately simulates the actual waveform of the substrate noise voltage of a large digital circuit by considering both power supply coupling (Ldi/dt) and capacitive coupling (CdV/dt). SWAN can simulate the actual time domain waveform of the substrate noise voltage, related to the real circuit operation. Its accuracy has been demonstrated with EPI-type substrates. For such substrates, the bulk can be considered as one bulk node such that the individual macromodels can be combined in parallel to construct a chip-level substrate macromodel. However, nowadays bulk-type substrates are more used. In this case a simple parallel combination of the macromodels may not be feasible for bulk-type substrates. Instead a three dimensional resistive (or RC) mesh might need to be considered, in combination with a multiple-input-multiple-output system formed by a network of switching noise sources and many sensing nodes in the analog circuits. The extension of SWAN to high-ohmic substrates, which is the subject of this paper, circumvents this complex problem by macromodeling the problem, making the approach applicable to large digital circuits. The interconnect is an important part of the circuit capacitance between V DD and V SS . For a 0.18 µm CMOS technology it was demonstrated that neglecting the interconnect underestimates the circuit capacitance by around 30 %. Interconnect will become more dominant in the future technologies. In this paper we take into account interconnect as part of this circuit capacitance as well as its impact on the supply current and resulting ground bounce. The paper is organized as follows. In section 2 we present the different sources of substrate noise. We also formulate conditions for which the substrate can be neglected for ground bounce in high-ohmic substrates. In section 3 we describe the extensions of the high-level substrate noise simulation methodology to bulk-type substrates. In section 4 the accuracy of the methodology is demonstrated on a 40K gates telecom circuit fabricated in 0.18 µm CMOS process and compared to measurements. 2. SOURCES OF SUBSTRATE NOISE In digital CMOS circuits substrate noise is caused by three mechanisms: coupling from the digital power supply, coupling from switching source–drain nodes and impact ionization in the MOSFET channel. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. DAC’04, June 7–11, 2004, San Diego, USA. Copyright 2004 ACM 1-58113-828-8/04/0006…$5.00. 50.3 854