IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308 _______________________________________________________________________________________ Volume: 03 Issue: 02 | Feb-2014, Available @ http://www.ijret.org 645 AN APPLICATION SPECIFIC RECONFIGURABLE ARCHITECTURE FOR FAULT TESTING AND DIAGNOSIS: A SURVEY A.R Kasetwar 1 , Gaurav Kumar 2 , S. M. Gulhane 3 1 Research Scholar,Dept. of Electronics & Tele communication, BDCE, Sewagram, Maharashtra, India 2 P.G student Dept. of Electronics & Tele communication, DBNCOET,Yavatmal, Maharashtra,India 3 Professor and Head of Dept. of Elect.& Telecomm.Engg, JDIET, Yavatmal, Maharashtra, India Abstract Now a day’s many VLSI designers are implementing different applications on real time with the use of FPGAs. Although they are working efficiently, they are not achieving their expected goals. This is only because of the faults which are occurring in the FPGA at the runtime of the application. Those faults are remaining in the circuitry as there is no provision for removal of those faults at application level. So there is a great need of detection & removal of faults. Mainly Interconnect faults, Logical F aults and Delay are the faults which reduces the performance of FPGA. Although the manufacturers are trying to decrease the fault present in the FPGA, it is very necessary to remove those faults at run time of the particular application. This paper includes the brief discussion about the occurrence of different faults and various methods to remove those faults. Key Words: Fault diagnosis, field-programmable gate array (FPGA), testing. --------------------------------------------------------------------***---------------------------------------------------------------------- 1. INTRODUCTION A Field Programmable Gate Array (FPGA) is a logic device that is used to implement a number of digital circuits. FPGA is widely used in many applications due to their reprogram ability, flexibility characteristic. It has also the advantage of short design & implementation cycles with low non- recurring engineering cost. As compare to Application specific integrated circuits (ASIC) FPGA results in faster design and debug cycle due to its reprogram ability. Though the density capability and speed of FPGA is increased, it becomes more vulnerable to various types of faults, but the FPGA test can be substantially more complex than application –Specific integrated circuit test. The basic architecture of FPGA consists of three major components: programmable logic blocks which implements the logic functions, programmable routing (interconnects) to implement these functions and IO blocks to make off-chip connections. We can Program FPGA for combination and sequential functions. All Programmable logic blocks (PLB) are Identical before programming. An illustration of typical FPGA architecture is shown in figure FIG.1Basic Architecture of FPGA FIG.2Typical Plb Structure Above diagram shows the typical structure of programmable logic blocks (PLB) ; it consist of a memory block that can function as look – up table(LUT) or RAM, number of flip- flop(FFs); and multiplying output logic. The LUT/RAM block may also contain special-purpose logic for arithmetic functions (counters, adders, multipliers, etc.). The RAM may be configured in various modes of operation like synchronous, asynchronous, single-port, dual-port, etc. The FFs can also be configured as latches, and may have programmable clock-enable, preset/clear, and data selector functions [2]. The manufacturer of FPGA is constantly trying to decrease the number of faults, which are present in their designed FPGA. Detection of faults and the type of faults, which is present in the circuit, is known as fault detection. Fault diagnosis, process locate the fault in the circuit and replace or remove the faulty circuit with a good one. In general, FPGA testing is of two types 1) Application Independent. 2) Application dependent. Application independent tests are performed at the manufacturer level. In this test, entire FPGA resources are tested for the presence of faults. The faults usually focused