International Journal of Ethics in Engineering & Management Education Website: www.ijeee.in (ISSN: 2348-4748, Volume 1, Issue 4, April 2014) 26 High Resolution Synchronous DPWM technique on FPGA using IODELAY1 block LINO M SAMUEL Mrs MEENA KV Mrs SAVITA Y PATIL Mrs SASIREKHA GVK Electronics department Electronics department Electronics department Electronics department The Oxford College of Engg, Bangalore The Oxford College of Engg, Bangalore The Oxford College of Engg, Bangalore The Oxford College of Engg, Bangalore lino.msamuel@gmail.com Abstract—Digital Pulse Width modulation or DPWM techniques are used widely now a day in converters and other controlled applications because of its better stability and efficiency. In DPWM we use bits for determining the width of a PWM pulse so in controlled application as the resolution increases so as the control over that application. This paper proposes a DPWM technique using IODELAYE1 block in vertex6 FPGA for obtaining high resolution PWM signal. Keywords—DPWM, Resolution, Converters I. INTRODUCTION In modern world need of energy harvesting techniques is increasing day by day and the outputs from these techniques are non-predictable. So in order to stabilize the output we use power converters like DC-DC converter [8][9]. DIGITAL pulse-width modulators (DPWMs) have become a basic building block in digital control architectures of any power converter. The DPWM frequency is mainly determined by the power converter operating conditions, whereas the DPWM resolution determines the accuracy in the output voltage/current control. Fig.1. waveform showing control over voltage As a consequence, the DPWM resolution has a direct impact in the power converter performance. Traditional DPWM implementations are based on counters and comparators, which generate the power converter gating signals according to several predefined thresholds. For these designs, the minimum on-time step is equal to the counter clock period. Its equivalent number of bits DPWM is DPWM= log 2 (f clk / f sw ) (1) where fSW is the DPWM frequency and fCLK is the counter clock frequency. Nowadays, power converters are evolving toward designs with higher switching frequencies in order to reduce the size of inductors and capacitors. Besides, for the digital implementation, the number of bits DPWM has to be higher than the A/D converter resolution to avoid limit cycling. As a consequence, an unfeasibly high clock frequency can result, increasing the complexity and the cost of the final implementation. Moreover, recent developments in semiconductor technology enable the use of higher switching frequencies through SiC and GaN power devices. This allows the design of power converters with reduced size and cost, and improved dynamic behaviour and power density, as shown in [3] and [4]. However, these designs require high-frequency high- resolution PWMs (HRPWMs) in order to take the most of the power converter. Most of DPWM techniques by delaying the reset signal are not fully synchronous. Asynchronous circuits make harder to perform static timing analysis and can result in glitching since controlling the logic and routing delays in an FPGA is more difficult than in ASIC implementations. Traditional designs of DPWM were based on the combination of counter and multiplexers. These designs often provide less bit resolution and jitter. Fig.2 traditional design based on counter A synchronous design, therefore, improves the reliability of the circuit and eases the design process. Besides, it makes the design more independent of the technology, easing the design portability. In design is based on the I/O delay element (IODELAYE1) available in the Virtex-6 FPGAs or Virtex-7 FPGA’s, and it provides higher resolution with a straight forward implementation.