978-1-4673-1036-9/12/$31.00 ©2012 IEEE 275 13th Int'l Symposium on Quality Electronic Design A Body-Voltage-Sensing-Based Short Pulse Reading Circuit for Spin-Torque Transfer RAMs (STT-RAMs) Fengbo Ren, Henry Park, Richard Dorrance, Yuta Toriyama, C.-K. Ken Yang, Dejan Marković Department of Electrical Engineering, University of California, Los Angeles, CA, USA E-mail: fren@ee.ucla.edu Abstract With scaling of CMOS and Magnetic Tunnel Junction (MTJ) devices, conventional low-current reading techniques for STT-RAMs face challenges in achieving reliability and performance improvements that are expected from scaled devices. The challenges arise from the increasing variability of the CMOS sensing current and the reduction in MTJ switching current. This paper proposes a short-pulse reading circuit, based on a body-voltage sensing scheme to mitigate the scaling issues. Compared to existing sensing techniques, our technique shows substantially higher read margin (RM) despite a much shorter sensing time. A narrow current pulse applied to an MTJ significantly reduces the probability of read disturbance. The RM analysis is validated by Monte- Carlo simulations in a 65-nm CMOS technology with both CMOS and MTJ variations considered. Simulation results show that our technique is able to provide over 300 mV RM at a GHz frequency across process-voltage-temperature (PVT) variations, while the reference designs require 4.3 ns and 2.3 ns sensing time for a 200 mV RM, respectively. The effective read energy per bit required by the proposed sensing circuit is around 195 fJ in the nominal case. Keywords Emerging memory, STT-RAM, sensing circuit, short-pulse reading, body-voltage sensing, read margin. 1. Introduction Over the last decade, extensive research has been carried out in the search of a scalable “universal memory.” Phase- Change RAM (PC-RAM) has been shown to be a viable replacement for Flash [1]. Resistive RAM (RRAM) is in its initial stage of exploration [2] and its benefits are yet to be seen. Recently, STT-RAM has been regarded as the front runner, because it can achieve a smaller cell size than SRAM, better performance than DRAM, the non-volatility of Flash, and better endurance (on the order of 10 16 read/write cycles) than Magnetoresistive RAM (MRAM) [3]-[5]. Compared to MRAM, another advantage of STT- RAM is that the switching current scales with device size [5] due to the nature of spin-torque transfer. With future scaling, the variation in CMOS devices is likely to continue to increase, and the critical current density (J C ) of the MTJ devices will decrease. These two effects combined will greatly impede the reliability of the MTJ read operation unless the reading is to be performed with levels of current that are comparable to those used for the write operation. Most existing STT-RAM reading schemes use a low- current reading (LCR) in which a sensing current smaller than the writing current is applied on the selected MTJ to avoid read disturbance [3], [6]-[8]. This approach leads to a sensing current that is strictly bounded by the long duration switching current (I C ) of the MTJ. Consequently, the scaling of J C will eventually challenge the viability of the LCR sensing scheme for a high-speed reading. To solve the problem, a short-pulse reading (SPR) scheme has been proposed in [9], where a sensing current that is similar in magnitude to the writing current is used to read the MTJ, but with a much shorter pulse width. However, no circuit implementation of the SPR scheme has been published thus far. Naturally, there has been no clear answer to what the best circuit structure to implement the SPR is. In this work, we propose an SPR circuit structure with a body-voltage sensing circuit. To study its suitability for the SPR, we analyze the read margin (RM) and performance of the proposed sensing circuit and compare them to those of the two reference designs [7], [8] under the proposed SPR structure. The analysis is validated by Monte-Carlo simulations in HSPICE using a 65-nm CMOS technology, considering both CMOS and MTJ variations. Results show that the proposed sensing circuit outperforms the reference designs by a large margin in sensing speed for the same energy. In the worst case of PVT variations, the proposed circuit can achieve a RM as high as 300 mV under a 1 V supply with only 0.78 ns of sensing time, while the reference designs require 4.3 ns and 2.3 ns to achieve a RM of 200 mV, respectively. The remainder of the paper is organized as follows. Section 2 introduces MTJ basics and discusses the SPR scheme. Implementation of the proposed SPR scheme is described in Section 3. Section 4 reviews the reference designs, introduces analysis metrics and the simulation setup. The comparison results and discussions are presented in Section 5. Section 6 concludes the paper. 2. Towards High-Speed Reading of STT-RAM Figure 1: The basic MTJ structure illustrating parallel and anti-parallel states and switching current.