© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim Phys. Status Solidi RRL 8, No. 3, 248–251 (2014) / DOI 10.1002/pssr.201308282 www.pss-rapid.com pss Wavy channel thin film transistor architecture for area efficient, high performance and low power displays Amir N. Hanna 1 , Galo A. Torres Sevilla 1 , Mohamed T. Ghoneim 1 , Aftab M. Hussain 1 , Rabab R. Bahabry 1 , Ahad Syed 2 , and Muhammad M. Hussain *, 1 1 Integrated Nanotechnology Lab, Electrical Engineering Program, Computer Electrical Mathematical Science and Engineering, King Abdullah University of Science and Technology, Thuwal 23955-6900, Saudi Arabia 2 Advanced Nanofabrication, Imaging and Characterization Core Facilities, King Abdullah University of Science and Technology, Thuwal 23955-6900, Saudi Arabia Received 15 November 2013, revised 15 December 2013, accepted 16 December 2013 Published online 20 December 2013 Keywords thin film transistors, displays, ZnO * Corresponding author: e-mail muhammadmustafa.hussain@kaust.edu.sa, Phone: +966 544 700 072, Fax: +1 888 908 5614 © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim 1 Introduction Increasing output current from thin film transistors (TFTs) with low total power consumption is essential for large-area high-resolution displays. This is specially important when considering TFT for backplane circuitry of organic light emitting diode (OLED) displays, where larger drive currents are required while maintaining low stand-by, or ‘OFF’ state, power consumption [1]. Also, large panel displays are in high demand from the consum- ers; therefore, achieving higher performance while main- taining low-cost integration of TFTs is critical. In accord- ance with the scaling trend of logic transistors, scaling the TFTs is a pursued method to increase the output current [2, 3]. However, lithographic scaling is expensive as well as it limits the transistor width resulting in reduced current. Also, as channel length is reduced, short-channel effects (SCE) are reported such as threshold voltage shifts and higher OFF state leakage, leading to degraded overall per- formance [4]. Therefore, a fin type feature vertically inte- grated wavy channel (WC) architecture can play critical role to increase the width, in the direction perpendicular to the substrate, without increasing the transistor area. We have previously shown the usefulness of this new architec- ture both for logic transistors and for polysilicon TFTs [5, 6]. This novel architecture is shown in Fig. 1(a), where it is shown vis-à-vis the planar counterpart in Fig. 1(b). Both devices consume the same chip area. The extra tran- sistor width, W extra , is equal to 2× the number of fins × fin height. The TFT architecture is back-gated as shown in the schematic for both the wavy and planar devices. We chose zinc oxide (ZnO) as the channel material since amorphous oxide semiconductors (AOS) are desirable for their high mobility, low leakage, transparency and their low- temperature deposition that allows integration on flexible substrates [7]. We also chose high-κ dielectric aluminum oxide (Al 2 O 3 ) as it forms a better interface with ZnO com- pared to conventional SiO 2 [8].We used atomic layer depo- We demonstrate a new thin film transistor (TFT) architecture that allows expansion of the device width using continuous fin features – termed as wavy channel (WC) architecture. This architecture allows expansion of transistor width in a di- rection perpendicular to the substrate, thus not consuming ex- tra chip area, achieving area efficiency. The devices have shown for a 13% increase in the device width resulting in a maximum 2.5× increase in ‘ON’ current value of the WCTFT, when compared to planar devices consuming the same chip area, while using atomic layer deposition based zinc oxide (ZnO) as the channel material. The WCTFT de- vices also maintain similar ‘OFF’ current value, ~ 100 pA, when compared to planar devices, thus not compromising on power consumption for performance which usually happens with larger width devices. This work offers an interesting op- portunity to use WCTFTs as backplane circuitry for large- area high-resolution display applications.