J. Parallel Distrib. Comput. 65 (2005) 743 –754 www.elsevier.com/locate/jpdc Hyperreconfigurable architectures and the partition into hypercontexts problem  Sebastian Lange, Martin Middendorf ∗ Parallel Computing and Complex Systems Group, Department of Computer Science, University of Leipzig, Augustusplatz 10/11, D-04109 Leipzig, Germany Received 2 August 2004; received in revised form 14 January 2005; accepted 23 January 2005 Available online 13 March 2005 Abstract Dynamically reconfigurable architectures or systems are able to reconfigure their function and/or structure to suit the changing needs of a computation during run time. The increasing flexibility of modern dynamically reconfigurable systems improves their adaptability to computational needs but also makes fast reconfiguration difficult because of the large amount of reconfiguration information which has to be transferred. However, even when a computation uses this flexibility it will not use it all the time. Therefore, we propose to make the potential for reconfiguration itself reconfigurable. Such architectures are called hyperreconfigurable. Different models of hyperreconfigurable architectures are proposed in this paper. We also study a fundamental problem that emerges on such architectures, namely, to determine for a given computation when and how the potential for reconfiguration should be changed during run time so that the reconfiguration overhead is minimal. It is shown that the general problem is NP-hard but fast polynomial time algorithms are given to solve this problem for special types of hyperreconfigurable architectures. We define two example hyperreconfigurable architectures and illustrate the introduced concepts for corresponding application problems. © 2005 Elsevier Inc. All rights reserved. Keywords: Dynamic reconfiguration; Reconfigurable architectures; Context partitioning; Reconfiguration costs 1. Introduction Dynamically reconfigurable architectures or systems can adapt their function and/or structure to suit the changing needs of a computation during run time (e.g., [2,3]). A principle problem of dynamically reconfigurable systems is the tradeoff between flexibility and the amount of informa- tion needed for reconfiguration to define the new state of the system. Moreover, the increasingly higher integration of reconfigurable hardware, e.g. reconfigurable circuits on an FPGA chip, requires increased bandwidths for transfer- ring the reconfiguration information. Modern FPGAs, for  This work was financed by the German Research Foundation (DFG) through the project “Models and Algorithms for Hyperreconfigurable Architectures” within the priority programme 1148 “Reconfigurable Com- puting Systems”. ∗ Corresponding author. Fax: +49 3419732329. E-mail addresses: langes@informatik.uni-leipzig.de (S. Lange), middendorf@informatik.uni-leipzig.de (M. Middendorf). 0743-7315/$ - see front matter © 2005 Elsevier Inc. All rights reserved. doi:10.1016/j.jpdc.2005.01.003 example, need several megabytes of reconfiguration data for a single reconfiguration step. This large amount of data trans- fer makes dynamic reconfigurations time critical operations, especially, for computations which exploit the full capacity of dynamically reconfigurable architectures by frequent re- configurations. Different approaches have been proposed in the litera- ture to cope with this problem. Dandalis and Prasanna [4] have applied off-line compression methods to the stream of reconfiguration bits. The compressed stream of reconfigura- tion bits can be loaded faster onto the chip. Additional hard- ware is necessary on the chip which allows to decompress the reconfiguration bit stream during run time before it is needed to define the next configuration. Another method for compression of the reconfiguration bit stream which is suit- able especially for the Xilinx XC6200 architecture has been described by Hauck et al. [7]. For Multi FPGA systems it has been proposed by Lee and Wong [11] to perform the re- configuration incrementally so that only parts of the FPGAs