IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308 __________________________________________________________________________________________ Volume: 03 Issue: 05 | May-2014, Available @ http://www.ijret.org 284 AN AREA AND POWER EFFICIENT ON CHIP COMMUNICATION ARCHITECTURES FOR IMAGE ENCRYPTION AND DECRYPTION Y.Amar Babu 1 , G.M.V.Prasad 2 1 Dept. of ECE, L.B.R. College of Engineering, Mylavaram, India 2 Principal, B.V.C. Institute of Technology and Science, Batlapalem, India Abstract The design of new electronic systems is getting more complex as more functionality is integrated into these systems. To design complex system, a predictable design flow is needed. A soft processor based System-on-Chip (SoC) is often mentioned as the hardware platform to be used in modern electronics systems for fast prototyping on FPGA. In this paper, a novel area and power efficient on chip communication architectures has been proposed for image encryption and decryption using single soft processor(Micro Blaze). Proposed System On Chip explores On chip Communication architectures features to efficiently implement the application. The SoC offers scalability and guarantees on the timing behavior when communicating data between various processing and storage elements. Proposed SoC has been implemented on Spartan6 FPGA and evaluated at 83.33MHz. It has occupied only 19% of resources available on target FPGA , consumes very low power. The proposed on chip communication architectures compared with device utilization on FPGA and power consumed. Keywords: SoC, FPGA, Encryption and Decryption, Micro Blaze -----------------------------------------------------------------------***------------------------------------------------------------------- 1. INTRODUCTION SoC architectures are used to provide the required computational power for novel embedded systems. The ITRS predicts that while manufacturing complex SoC will be feasible, the production cost will grow rapidly as the costs of masks is raising drastically. The growing complexity of embedded systems leads to a large in their development effort. At the same time, the market dynamics for these systems push for shorter and shorter development times. The NRE cost associated with the design and tools of complex chips is growing rapidly. To address these issues, a platform based design methodology is proposed. The main objective of this design methodology is to increase the re-use of soft cores and IPs. The SoC consists of both hardware, and the software controlling the soft processor or DSP cores, peripherals and interfaces. The design flow for a SoC aims to develop this hardware and software in parallel. Most SoCs are developed from pre-designed hardware blocks for the hardware, together with the software drivers that control their operation. The hardware blocks are put together using EDA tools. The software modules are integrated using a Software development environment. In this paper, a novel soft processor based SoC architecture is proposed for Image encryption and decryption, which is based on shared processor local bus (PLB) and developed using Xilinx Platform Studio (XPS)[1][2]. Proposed SoC has three layers, hardware layer which is based on soft processor (Micro Blaze), Standalone OS layer which has low level drivers for different controllers and interfaces and application layer which is developed using above two layers as shown in Figure1[3]. 2. MICRO BLAZE SOFT PROCESSOR The micro blaze embedded processor soft core is a reduced instruction set computer (RISC) optimized for implementation in Xilinx Field Programmable Gate Arrays (FPGAs). Compared to other general purpose processors, micro blaze is quite flexible with a few configurable parts and capable of being extended by customized co-processors. There are a number of on-chip communication strategies available including a variety of memory interfaces. The operating frequency of micro blaze on spartan-6 SP605 kit is 83.33Mhz. Hence we use micro blaze soft-core processor in order to develop hardware platform for JPEG compression application. Micro blaze processor has an instruction decoding unit, 32x32 bit general purpose register file, arithmetic unit and special