IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308 __________________________________________________________________________________________ Volume: 02 Issue: 12 | Dec-2013, Available @ http://www.ijret.org 151 RUN TIME DYNAMIC PARTIAL RECONFIGURATION USING MICROBLAZE SOFT CORE PROCESSOR FOR DSP APPLICATIONS C. V. Borkute 1 , A. Y. Deshmukh 2 1 Research Student, G.H.Raisoni College of EngineeringNagpur, Maharshtra, India, cvborkute@gmail.com 2 Deputy Director & Dean(Planning & Quality Assurance) G.H.Raisoni College of Engineering Nagpur, Maharashtra, and India, aydeshmukh@gmail.com Abstract DSP Application requires a fast computations & flexibility of the design. Partial Reconfiguration (PR) is an advanced technique, which improves the flexibility of FPGAs by allowing portions of a design to be reconfigured at runtime by overwriting parts of the configuration memory. In this paper we are using microblaze soft core processor & ICAP Port to reconfigure the FPGA at runtime. ICAP is accessed through a light-weight custom IP which requires bit stream length, go, and done signal to interface to a system that provides partial bit stream data. The partial bit stream is provided by the processor system by reading the partial bit files from the compact flash card. Our targeted DSP application is matrix multiplication; we are reconfiguring design by changing partial modules at run time. To change the partial bit stream we interfaces a microblaze Soft processor & using a UART interface.ISE13.1 & PlanAhead is used for partial reconfiguration of FPGA .EDK is used for microblaze soft processor design & ICAP Interface .The simulation is done using Chip Scope Logic Analyzer & the complete hardware implementation is done on Xilinx VIRTEX -6 ML605 Platform. Keywords — PlanAhead, EDK, Dynamic partial reconfiguration, ICAP, Matrix multiplication, Chipscope pro analysis, DSP application, Microblaze processor ---------------------------------------------------------------------***--------------------------------------------------------------------- 1. INTRODUCTION Xilinx partial reconfiguration extends the inherent flexibility of the FPGA by allowing specific regions of the FPGA to be reprogrammed with new functionality while applications continue to run in the remainder of the device. Partial reconfiguration addresses three fundamental needs by enabling [1] • Reduce cost and/or board space • Change a design in the field • Reduce power consumption The two most prevalent user problems, addressed by partial reconfiguration are: • Fitting more logic into an existing device • Fitting a design into a smaller, less expensive device Historically, designers have spent days, if not weeks, trying new implementation switches, reworking code, and re- engineering solutions to squeeze them into the smallest possible FPGA. Partial reconfiguration enables these designers to reduce the size of their designs by dynamically time-multiplexing portions of the available hardware resources [2]. The ability to load functions on an as-needed basis also reduces the amount of idle logic, thereby saving additional space. In the past, changing a design in the field required new placement and routing of the design and the delivery of a full configuration file. The engineer also had to shut the system down while making the change. In contrast, when using partial reconfiguration, the designer needs only to place and route the modified function in context with the already-verified remainder of the design, then deliver this new partial image to a system in the field. Moreover, the engineer can dynamically insert new functions while the system is up and running, improving system up-time [3]. Thus, mutually exclusive functions can be plugged into the same space without having to redesign the system or move to a bigger device, Power consumption has become a primary concern for today's designers. Like size and cost, it is a metric with strict limits in most systems. However, as FPGA designs grow in size and complexity, they consume more power. While synthesis and implementation tools coupled with appropriate design techniques can help reduce power consumption, partial reconfiguration implementations can further reduce static and dynamic power. One way to reduce static power is to simply use a smaller device. With partial reconfiguration, designers can essentially time slice the FPGA and run parts of their design independently. The design then requires a much smaller device or fewer devices because not every part of the design is needed 100% of the time. Partial reconfiguration also