IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 3, MARCH 2010 557 Digital Controller for DVS-Enabled DC–DC Converter Mukti Barai, Member, IEEE, Sabyasachi Sengupta, and Jayanta Biswas Abstract—A high-frequency digital controller that includes an optimized analog–digital converter (ADC) with a novel formulation of digital error value based on target clock frequency and converter output voltage is presented in this paper. A programmable look-up table-based digital compensator is implemented for fast process- ing the feedback error. Limitations of a hybrid digital pulsewidth modulator (DPWM) at high frequency are addressed and solved by an edge-triggered logic. Support for process, voltage, and tem- perature variations is incorporated in the integrated design. Target clock frequency denotes the frequency of the signal which is driven by dynamic voltage scaling (DVS) processor and corresponds to the reference value of the regulated output voltage. This work re- alizes the classical digital controller design implementation of a target frequency to minimum required regulated voltage for DVS- enabled adaptive dc-dc converter. A synchronous buck converter of 1 MHz switching frequency and the proposed delay-line-based op- timized ADC have been fabricated for realizing and verifying the complete digital controller on a field-programmable gate array- based closed-loop prototype. Experimental results are presented, which demonstrate the fast dynamic response achieved for target clock frequency in the range of 6–16 MHz, corresponding to the regulated output voltage range of 1.6–3.2 V. The complete design of digital controller has been implemented in 0.5 μm CMOS tech- nology using Cadence and Synopsys tools. The active on-chip area of the proposed delay-line ADC, digital compensator, and edge- triggered hybrid DPWM are 0.08, 0.28, and 0.07 mm 2 respectively. Index Terms—Analog–digital converter (ADC), dc–dc power converter, delay line, digital controller, dynamic voltage scaling (DVS). I. INTRODUCTION P ROLIFERATION of portable electronic equipment has led to the study and development of several power management techniques for optimizing the battery power source. Power con- sumption in a portable electronic device is dominated by the dynamic power consumption. Dynamic power consumption is proportional to the product of clock frequency and square of the supply voltage. A power management technique that sig- nificantly increases energy savings by scaling down the supply voltage until the chip meets its specific performance (desired speed) requirements [1], is known as dynamic voltage scaling (DVS). Practical implementation of DVS requires two key com- ponents: a general purpose processor that operates over a wide range of operating voltage and a regulation loop to provide the minimum required voltage for the desired speed of operation. Manuscript received December 4, 2008; revised May 31, 2009. Current ver- sion published March 31, 2010. Recommended for publication by Associate Editor F. L. Luo. M. Barai and S. Sengupta are with the Department of Electrical Engineering, Indian Institute of Technology Kharagpur, Kharagpur 721302, India (e-mail: mukti@ee.iitkgp.ernet.in; ssg@ee.iitkgp.ernet.in). J. Biswas is with the International Institute of Information Technology, Bangalore 560100, India (e-mail: jayanta.biswas@iiitb.ac.in). Digital Object Identifier 10.1109/TPEL.2009.2030195 Fig. 1. Digital controller in closed loop with dc–dc converter. Processors used for implementing DVS require a voltage con- verter that is different from the standard voltage regulator con- cept because the converter must also track the operating voltage when a new clock frequency is requested [2], in addition to regulating voltage for a given clock frequency. DC–dc switching converters are mainly chosen for the regula- tion loop in DVS because of their high efficiency. DVS [3]–[7] presents a set of technical challenges to the dc–dc switching converters to satisfy static and dynamic regulation, fast dynamic response and high efficiency requirements over a wide range of regulated output voltage for the corresponding range of target clock frequency. Control aspects of the dc–dc switching con- verter become important to meet the technical challenges set by DVS. Digital controllers are increasingly being used in DVS because of their advantages including the ability to perform sophisticated control schemes, low power consumption, relia- bility, reconfiguration, flexibility, elimination of precise analog components and ease of integration in interfacing with other digital systems. However, some challenges still remain for us- ing digitally controlled dc–dc converters in DVS applications. The demand for high resolution requirement to satisfy the tight regulation requirements of the converter and the high speed required to satisfy a wide range of dynamics of the converter are some of these remaining challenges in the digital controller architecture. The digital controller architecture that provides minimum required output voltage for a target frequency, meets the requirements of optimum power consumption. The design process of a digitally controlled converter needs selection and optimization of each block of a digital controller architecture in a closed-loop with a dc–dc switching converter as shown in Fig. 1. Systems-on-chip (SOC) designs are becoming larger and more complex with increased number of complex applications on a single chip and effective power management technique is es- sential for successful SOC designs. Digital design approach that 0885-8993/$26.00 © 2009 IEEE